LCMXO256C-3TN100 - Brand New LATTICE Programmable Logic Device (CPLDs/FPGAs)
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Description
The LCMXO256C-3TN100 is a programmable logic device designed to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs. It is optimized for tasks such as glue logic, bus bridging, bus interfacing, power-up control, and control logic. This device combines the best features of CPLD and FPGA devices into a single chip.
Specifications and features
- Non-volatile, infinitely reconfigurable
- Instant-on power-up in microseconds
- Single chip design, no external configuration memory required
- Excellent design security with no bit stream to intercept
- Reconfigure SRAM based logic in milliseconds
- SRAM and non-volatile memory programmable through JTAG port
- Supports background programming of non-volatile memory
- Sleep mode allows up to 100x static current reduction
- TransFR™ Reconfiguration (TFR) enables in-field logic update while system operates
- High I/O to logic density ratio with 256 to 2280 LUT4s and 73 to 271 I/Os
- Extensive package options and density migration support
- Lead free/RoHS compliant packaging
- Embedded and distributed memory with up to 27.6 Kbits sysMEM™ Embedded Block RAM and up to 7.5 Kbits distributed RAM
- Dedicated FIFO control logic
- Flexible I/O buffer with programmable sysIO™ buffer supporting various interfaces including LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, and RSDS
- sysCLOCK™ PLLs with clock multiply, divide, and phase shifting capabilities
- System level support with IEEE Standard 1149.1 Boundary Scan, onboard oscillator, and compatibility with various power supply voltages
- IEEE 1532 compliant in-system programming
Application Scenarios
- Glue logic
- Bus bridging
- Bus interfacing
- Power-up control
- Control logic
Comparison
Advantages- Combines the best features of CPLDs and low capacity FPGAs
- Non-volatile and infinitely reconfigurable
- Instant-on power-up
- No external configuration memory required
- Excellent design security
- Supports background programming
- Sleep mode for power reduction
- Supports in-field logic update
- High I/O to logic density ratio
- Extensive package options
- Lead free/RoHS compliant packaging
- Embedded and distributed memory options
- Flexible I/O buffer supporting various interfaces
- sysCLOCK™ PLLs for precise clock control
- System level support with IEEE Standard 1149.1 Boundary Scan and in-system programming
Disadvantages- Limited capacity compared to larger FPGAs
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Similar parts: 2518 , Click to view
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
- - DHL Express: 3-7 business days
- - DHL eCommerce: 12-22 business days
- - FedEx International Priority: 3-7 business days
- - EMS: 10-15 business days
Shipping fee:
- - Automatic Email notification (above 5 times)
- - View in your order page
Shipping option:
DHL, FedEx, EMS, SF Express, and Registered Air MailShipping tracking:
- - Automatic Email notification (above 5 times)
- - View in your order page
How to Buy:
- - In-stock, Add to cart > Check out > Submit order > Complete payment >Delivery.
- - Inquiry, Add to inquiry sheet/Submit bom/inquire file/Send email us > Quote > Place order > Complete payment >Delivery.
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Payment:
- - Paypal,Credit Card includes Visa, Master, American Express.
- - Wire transfer, include Local bank transfer.
- - Western Union.
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- Datasheet: Download LCMXO256C-3TN100
- Chipdatas Part: CD87-LCMXO256C-3TN100
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/09/29 03:09 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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The fee is charged according to the rule of PayPal.
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The fee is charged according to the rule of PayPal.
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Western Union charge US$0.00 banking fee.
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We recommend to use bank transfer for large orders to save on handling fees.
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DHL(www.dhl.com)
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FedEx(www.fedex.com)
$40 limited time offer. -
Registered Mail(www.singpost.com)
Free shipping without minimum order.