Description

The EPM9320ARC208-10N is a member of the MAX 9000 family, a high-density, high-performance, in-system-programmable Electronic Programmable Logic Devices (EPLDs). These EPLDs are based on the third-generation MAX architecture, fabricated on advanced CMOS technology, and come with EEPROM-based programmable logic. The MAX 9000 family has a range of 6,000 to 12,000 usable gates, pin-to-pin delays up to 10 ns, and counter speeds up to 144 MHz.

Specifications and features

• High-performance CMOS EEPROM-based programmable logic devices (PLDs).
• Built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface for in-system programmability (ISP).
• Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990.
• High-density EPLD family ranging from 6,000 to 12,000 usable gates.
• Pin-to-pin logic delays as fast as 10 ns with counter frequencies of up to 144 MHz.
• Fully compliant with the PCI SIG’s PCI Local Bus Specification, Revision 2.2.
• Dual-output macrocell for independent use of combinatorial and registered logic.
• FastTrack Interconnect for fast and predictable interconnect delays.
• Input/output registers with clear and clock enable on all I/O pins.
• Programmable output slew-rate control to reduce switching noise.
• MultiVolt I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices.
• Configurable expander product-term distribution allowing up to 32 product terms per macrocell.
• Programmable power-saving mode for more than 50% power reduction in each macrocell.
• Programmable macrocell flip-flops with individual clear, preset, clock, and clock enable controls.
• Programmable security bit for protection of proprietary designs.
• Software design support and automatic place-and-route provided by Altera’s MAX+PLUS II development system on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations.
• Additional design entry and simulation support provided by EDIF 200 and 300 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest.
• Programming support with Altera’s Master Programming Unit (MPU), BitBlasterTM serial download cable, ByteBlasterTM parallel port download cable, and ByteBlasterMVTM parallel port download cable, as well as programming hardware from third-party manufacturers.
• Offered in a variety of package options with 84 to 356 pins.

Application Scenarios

The EPM9320ARC208-10N is designed to be used in various electronic products that require a programmable logic device. The device can be programmed to implement custom logic functions, making it suitable for a wide range of applications such as automotive, industrial control systems, aerospace, and telecommunications, among others.

Comparison

• High-density EPLD family ranging from 6,000 to 12,000 usable gates, thus suitable for complex designs.
• Compliant with the PCI SIG's PCI Local Bus Specification, Revision 2.2.
• Programmable security bit for protection of proprietary designs.
• Configurable expander product-term distribution allowing up to 32 product terms per macrocell.

• The device is relatively expensive compared to other programmable logic devices.
• May not be suitable for low-cost and low-power applications.
• The device requires programming before use, which may add complexity to the design process.