Description

EPM7160STI100-10N is a CPLD - Complex Programmable Logic Device belonging to the MAX 7000 high-density, high-performance PLDs family, based on Altera’s second-generation MAX architecture. The MAX 7000 provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. 

Specifications and features

Features:
■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
■ PCI-compliant devices available

Application Scenarios

The EPM7160STI100-10N can be used in various applications such as digital signal processing, video and image processing, communication systems, and control systems. This device is also suitable for applications requiring high-speed signal processing, low-power consumption, and small package size.

Comparison

• High-density and high-performance
• EEPROM-based programmable logic devices
• Low-power consumption
• 5.0-V in-system programmability (ISP)
• PCI-compliant devices available

• This model is not suitable for applications that require extremely low power consumption.
• The number of usable gates is relatively limited compared to other models in the MAX series.