Description

The ISPLSI2096VE135LT128I is a high-density programmable logic device (PLD) that features in-system programmability and non-volatile reprogrammability. It contains 96 registers, six dedicated input pins, three dedicated clock input pins, two dedicated global OE input pins, and a global routing pool (GRP) that provides complete interconnectivity. This device is 100% IEEE 1149.1 boundary scan testable, allowing for easy testing and verification.

Specifications and Features

• SuperFAST High Density Programmable Logic
• 4000 PLD Gates
• 96 I/O Pins, Six Dedicated Inputs
• 96 Registers
• High Speed Global Interconnect
• Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
• Small Logic Block Size for Random Logic
• 100% Functional, JEDEC and Pinout Compatible with ispLSI 2096V Devices
• Pinout Compatible with ispLSI 2192VE
• 3.3V Low Voltage 2096 Architecture
• Interfaces with Standard 5V TTL Devices
• High Performance E2CMOS® Technology
• fmax = 250MHz Maximum Operating Frequency
• tpd = 4.0ns Propagation Delay
• Electrically Erasable and Reprogrammable
• Non-Volatile
• 100% Tested at Time of Manufacture
• Unused Product Term Shutdown Saves Power
• In-System Programmable
• 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)
• Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
• Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
• Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 Boundary Scan Testable
• The Ease of Use and Fast System Speed of PLDs with the Density and Flexibility of FPGAs
• Enhanced Pin Locking Capability
• Three Dedicated Clock Input Pins
• Synchronous and Asynchronous Clocks
• Programmable Output Slew Rate Control
• Flexible Pin Placement
• Optimized Global Routing Pool Provides Global Interconnectivity
• Lead-Free Package Options

Application Scenarios

The ISPLSI2096VE135LT128I is suitable for a wide range of applications, including but not limited to:

• Embedded Systems
• Communication Devices
• Consumer Electronics
• Industrial Control Systems
• Automotive Electronics

Comparison

- High density programmable logic with 4000 PLD gates
- In-system programmability and non-volatile reprogrammability
- Wide input gating for fast counters, state machines, address decoders, etc.
- 100% IEEE 1149.1 boundary scan testable

- Requires compatible devices with 3.3V low voltage architecture
- Lead-free package options may have certain limitations
- Programmable output slew rate control may require additional configuration