Description

The C2520C-R56J is an IC chip product category that features the PI6C2520, a phase-locked loop (PLL) clock driver ideal for low-skew, low-jitter clock signal distribution for networking applications. It features a near-zero propagation delay from the CLK_IN input to any clock output, which enables the distributed clock input, providing 5 banks of 4 clocks and an extra clock for feedback.

Specifications and features

• Low-Noise Phase-Locked Loop Clock Distribution
• Allows Clock Input to have Spread Spectrum modulation for EMI reduction. The clock outputs track the Clock Input modulation.
• Maximum clock frequency of 125 MHz.
• Zero Input-to-Output delay.
• Low jitter: Cycle-to-Cycle jitter –100ps max
• On-chip series damping resistor at clock output drivers for low noise and EMI reduction.
• Operates at 3.3V VCC.
• Output-to-Output skew less than 200ps.
• Package: Plastic 56-pin TSSOP (A).

Application Scenarios

The C2520C-R56J is ideal for networking applications where a low-skew, low-jitter clock signal is required with a maximum clock frequency of 125 MHz and a zero Input-to-Output delay feature. Its on-chip series damping resistor also makes it an efficient IC chip component for low noise and EMI reduction in network applications.

Comparison

• Near-zero propagation delay from the CLK_IN input to any clock output.
• Low-Noise Phase-Locked Loop Clock Distribution feature that allows clock input to have Spread Spectrum modulation for EMI reduction. The clock outputs track the Clock Input modulation.
• Low jitter: Cycle-to-Cycle jitter –100ps max. Operates at 3.3V VCC.
• On-chip series damping resistor at clock output drivers for low noise and EMI reduction.

• Ouput-to-Output Skew is limited to less than 200ps.