Description

The PM73122-BIAP is an AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) IC Chip. It provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. The device arbitrates access to an external SRAM for storage of configuration, user data, and statistics. It also offers a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra provides a software device control package for the AAL1gator-32 device.

Specifications and features

• Compliant with the ATM Forum's Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1
• Supports Dynamic Bandwidth Circuit Emulation Services (DBCES)
• Provides AAL1 segmentation and reassembly of various line interfaces including E1, T1, E3, DS3, and STS-1
• Supports Scalable Bandwidth Interconnect (SBI) Interface for up to 32 T1, E1, or 2 DS3 links
• Provides UTOPIA level 2 Interface with various modes of operation
• Supports up to 1024 Virtual Channels (VC)
• Allows transparent transmission of Common Channel Signaling (CCS) and Channel Associated Signaling (CAS)
• Provides per-VC data and signaling conditioning options
• Supports multicast connections

Application Scenarios

• Multi-service ATM Switch
• ATM Access Concentrator
• Digital Cross Connect
• Computer Telephony Chassis with ATM infrastructure
• Wireless Local Loop Back Haul
• ATM Passive Optical Network Equipment

Comparison

- Supports various line interface access

- Compliant with industry standards

- Provides flexibility in configuration and management

- Supports a large number of Virtual Channels

- Supports transparent transmission of signaling

- Requires external SRAM for storage

- Limited to AAL1 segmentation and reassembly