Description

The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns.

Features include 7.5 ns pin-to-pin logic delays on all pins, f CNT to 125 MHz, 72 macrocells with 1,600 usable gates, up to 72 user I/O pins, and 5 V in-system programmable (ISP) with an endurance of 10,000 program/erase cycles. It also has an enhanced pin-locking architecture, flexible 36V18 Function Block, extensive IEEE Std 1149.1 boundary-scan (JTAG) support, and programmable power reduction mode in each macrocell. The XC9572 is available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages.

Specifications and features

- 7.5 ns pin-to-pin logic delays on all pins

- f CNT to 125 MHz

- 72 macrocells with 1,600 usable gates

- Up to 72 user I/O pins

- 5 V in-system programmable (ISP)

- Endurance of 10,000 program/erase cycles

- Enhanced pin-locking architecture

- Flexible 36V18 Function Block

- Extensive IEEE Std 1149.1 boundary-scan (JTAG) support

- Programmable power reduction mode in each macrocell

- Slew rate control on individual outputs

- User programmable ground pin capability

- Extended pattern security features for design protection

- High-drive 24 mA outputs

- 3.3 V or 5 V I/O capability

- Advanced CMOS 5V FastFLASH technology

- Supports parallel programming of more than one XC9500 concurrently

- Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages

Application Scenarios

The XC9572 is suitable for various general purpose logic integration applications, including but not limited to:

- Electronic devices

- Communication systems

- Industrial automation

- Automotive electronics

- Medical equipment

Comparison

Advantages:

- High-performance CPLD

- Advanced in-system programming and test capabilities

- Wide range of package options

- Extensive features and specifications

Disadvantages:

- Limited usable gates

- Propagation delays of 7.5 ns