Description

The OR3T556PS240 is an FPGA model belonging to the ORCA Series 3 family of SRAM-based FPGAs. It is a high-performance, synthesizable, and cost-effective IC chip manufactured using 0.3 µm (OR3T) metal technology. This electronic component is designed to deliver complete routability, enhance logic requirements, and increase system speed. The chip contains many new innovations and enhancements, making it the ideal choice for today's high-speed designs and tomorrow's systems on a single chip.

Specifications and features

• Technology: 0.3 µm (OR3T) 4-level metal technology
• Delay: 1.1 ns with -7 speed grade in 0.3 µm
• Architecture: Same basic architecture as lower-voltage, advanced process technology Series 3 architectures
• Usable gates: up to 186,000
• User I/Os: up to 452
• I/O clamping diodes: Pin selectable
• Function unit (PFU) architecture: Twin-quad programmable
• Number of LUTs per PFU: Eight 16-bit look-up tables (LUTs) per PFU
• User registers per PFU: Nine, with programmable clock enable and local set/reset, plus a global set/reset that can be disabled per PFU
• Flexible input structure (FINS) of the PFUs: provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs
• Fast-carry logic and routing: to adjacent PFUs for nibble-, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out
• Softwired LUTs (SWL): allow fast cascading of up to three levels of LUT logic in a single PFU for up to 40% speed improvement
• Supplemental logic and interconnect cell (SLIC): provides 3-statable buffers, up to 10-bit decoder, and PAL-like AND-OR with optional INVERT in each programmable logic cell (PLC), with over 50% speed improvement typical
• Routing resources: Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide faster place and route implementations and less routing delay
• Input levels: TTL or CMOS input levels programmable per pin for the OR3Cxx (5.0 V) devices
• Drive capability: Individually programmable drive capability of 12 mA sink/6 mA source or 6 mA sink/3 mA source
• Built-in boundary scan: IEEE †1149.1 JTAG and TS_ALL testability function to 3-state all I/O pins
• System clock routing: Enhanced system clock routing for low skew, high-speed clocks originating on-chip or at any I/O
• ExpressCLK inputs: Up to four ExpressCLK inputs allow extremely fast clocking of signals on-and off-chip plus access to internal general clock routing
• StopCLK feature: Glitchlessly stop/start ExpressCLKs independently by user command
• Programmable I/O (PIO): Fast-capture input latch and input flip-flop (FF) latch for reduced input setup time and zero hold time

Application Scenarios

The OR3T556PS240 FPGA is suitable for use in a wide range of applications, including robotics, aerospace, military, automotive, industrial automation, and consumer electronics. It is ideal for applications that require high-performance, low power consumption, and complete routability.

Comparison

• High-performance and cost-effective due to built-in system-level features.
• Contains many patented enhancements that deliver complete routability and increase system speed.
• Softwired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU for up to 40% speed improvement.
• Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder, and PAL-like AND-OR with optional INVERT in each programmable logic cell (PLC), with over 50% speed improvement typical.
• Flexible input structure (FINS) of the PFUs provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs.

• Not suitable for low-power applications.
• Does not support high voltage applications above 5 V.
• May be difficult to program for beginners due to its complexity.