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Description
The SCM34PT is an electronic component model that belongs to the IC Chips product category. It is part of the LatticeSC family of FPGAs, which combines a high-performance FPGA fabric, high-speed SERDES, high-performance I/Os, and large embedded RAM in a single industry-leading architecture. This FPGA family is fabricated using state-of-the-art technology to provide one of the highest performing FPGAs in the industry.
Specifications and Features
The SCM34PT has the following specifications and features:
- High Performance FPGA Fabric
- 15K to 115K four input Look-up Tables (LUT4s)
- 139 to 942 I/Os
- 700MHz global clock; 1GHz edge clocks
- 4 to 32 High-Speed SERDES and flexiPCS™ (per Device)
- Performance ranging from 600Mbps to 3.8Gbps
- Excellent Rx jitter tolerance (0.8UI at 3.125Gbps)
- Low Tx jitter (0.25UI typical at 3.125Gbps)
- Built-in Pre-emphasis and equalization
- Low power (typically 105mW per channel)
- Embedded Physical Coding Sublayer (PCS) provides pre-engineered implementation for various standards such as GbE, XAUI, PCI Express, SONET, Serial RapidIO, 1G Fibre Channel, and 2G Fibre Channel
- 2Gbps High Performance PURESPEED™ I/O
- Supports differential I/O up to 2Gbps DDR (1GHz Clock) and single-ended memory interfaces up to 800Mbps
- 144 Tap programmable Input Delay (INDEL) block on every I/O dynamically aligns data to the clock for robust performance
- Supports various electrical standards such as LVCMOS, LVTTL, SSTL, HSTL, PCI, PCI-X, LVDS, Mini-LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS, and Hypertransport
- Programmable On Die Termination (ODT) with Thevenin Equivalent and low power VTT termination options
- 1 to 7.8 Mbits memory
- True Dual Port/Pseudo Dual Port/Single Port
- Dedicated FIFO logic for all block RAM
- Additional 240K to 1.8Mbits distributed RAM
- sysCLOCK™ Network with eight analog PLLs per device and extensive clocking network
- Masked Array for Cost Optimization (MACO™) Blocks for low power, low-cost system-level integration
- High Performance System Bus that connects FPGA elements together with a standard bus framework
- System Level Support including IEEE standard 1149.1 Boundary Scan, ispTRACY™ internal logic analyzer, IEEE Standard 1532 in-system configuration, 1.2V and 1.0V operation, onboard oscillator for initialization and general use, embedded PowerPC microprocessor interface, low-cost wire-bond, and high pin count flip-chip packaging, and low-cost SPI Flash RAM configuration
Application Scenarios
The SCM34PT can be used in a wide range of applications such as:
- FPGA-based systems
- High-performance computing
- Networking equipment
- Communication systems
- Data processing
- Embedded systems
Comparison
Advantages:
- High-performance FPGA fabric
- High-speed SERDES
- Large embedded RAM
- Support for various electrical standards
- Low power consumption
- Pre-engineered implementation for various standards
- Extensive clocking network
- System level support
Disadvantages:
- Specific to the LatticeSC family of FPGAs
- May not be suitable for all applications
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Datasheet
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Shopping guide
Delivery period:
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Additional Information
- Datasheet: Download SCM34PT
- Chipdatas Part: CD94-SCM34PT
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/09/28 17:26 +0800
Refund
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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