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**The MC14015B dual 4–bit static shift register is constructed with MOS
P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4–state serial–input/parallel–output registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D master–slave flip–flops. Data is shifted from one stage to the next during the positive–going clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial–to–parallel conversion where low power dissipation and/or noise immunity is desired.**
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going edge of the clock pulse.
• Capable of Driving Two Low–power TTL Loads or One Low–power Schottky
TTL Load Over the Rated Temperature Range. -
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- Datasheet: Download MC14015BFJA
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- Last Updated: 2024/09/17 03:19 +0800
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