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Description
The C2520C-22NJ is a low-skew, low-jitter, phase-locked loop (PLL) clock driver designed for Networking Applications. It distributes low-noise clock signals and allows clock input to have Spread Spectrum modulation for EMI reduction. With a maximum clock frequency of 125 MHz, it provides zero input-to-output delay and low jitter. The C2520C-22NJ operates at 3.3V VCC and comes in a plastic 56-pin TSSOP (A) package.Specifications and features
- Low-Noise Phase-Locked Loop Clock Distribution - Allows Clock Input to have Spread Spectrum modulation for EMI reduction - Maximum clock frequency of 125 MHz - Zero Input-to-Output delay - Low jitter: Cycle-to-Cycle jitter –100ps max - On-chip series damping resistor at clock output drivers for low noise and EMI reduction - Operates at 3.3V VCC - Output-to-Output skew less than 200ps - Package: Plastic 56-pin TSSOP (A)Application Scenarios
The C2520C-22NJ is ideal for Networking Applications that require low-skew and low-jitter clock distribution. It can be used in various networking devices such as routers, switches, and servers.Comparison
Advantages- Low-noise clock distribution - Spread Spectrum modulation for EMI reduction - Zero input-to-output delay - Low jitter - On-chip series damping resistor for low noise and EMI reductionDisadvantages- Output-to-Output skew limited to less than 200ps - Operates at 3.3V VCC -
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Datasheet
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Shopping guide
Delivery period:
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Additional Information
- Datasheet: Download C2520C-22NJ
- Chipdatas Part: CD88-C2520C-22NJ
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/09/20 05:42 +0800
Refund
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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The fee is charged according to the rule of PayPal.
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