EPC16QI100N - Brand New Intel / Altera Memory - Configuration Proms for FPGAs
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In Stock:
946,
Ready for Immediate Shipping
Brand:Intel / Altera
Chipdatas Part No.:CD87-EPC16QI100N
Manufacturer Part No.:EPC16QI100N
Datecode:09+
Package:100-BQFP
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Description
The Altera enhanced configuration device (model: EPC16QI100N) is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. It consists of a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can also be used to store additional processor code or data that can be accessed via the external flash interface after FPGA configuration is complete.
Specifications and Features
- Enhanced configuration devices include EPC4, EPC8, and EPC16 devices.
- Single-chip configuration solution for Stratix® series, Cyclone™ series, APEX™ II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), Mercury™, ACEX® 1K, and FLEX® 10K (FLEX 10KE and FLEX 10KA) devices.
- Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage.
- On-chip decompression feature almost doubles the effective configuration density.
- Standard flash die and a controller die combined into single stacked chip package.
- External flash interface supports parallel programming of flash and external processor access to unused portions of memory.
- Flash memory block/sector protection capability via external flash interface.
- Supported in EPC16 and EPC4 devices.
- Page mode support for remote and local reconfiguration with up to eight configurations for the entire system.
- Compatible with Stratix series Remote System Configuration feature.
- Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data output per DCLK cycle.
- Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs.
- Pin-selectable 2-ms or 100-ms power-on reset (POR) time.
- Configuration clock supports programmable input source and frequency synthesis.
- Multiple configuration clock sources supported (internal oscillator and external clock input pin).
- External clock source with frequencies up to 133 MHz.
- Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of 33, 50, and 66 MHz.
- Clock synthesis supported via user programmable divide counter.
- Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA® packages.
- Vertical migration between all devices supported in the 100-pin PQFP package.
- Supply voltage of 3.3 V (core and I/O).
Application Scenarios
The Altera enhanced configuration device is designed for use in high-density FPGA systems that require fast and efficient configuration. It is suitable for a wide range of applications, including telecommunications, automotive, consumer electronics, and industrial control.
Comparison
Advantages- Single-chip configuration solution for multiple FPGA series
- On-chip decompression feature to increase configuration density
- Supports various configuration modes and clock sources
- Available in different package options
Disadvantages- Limited supply voltage of 3.3 V
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Additional Information
- Datasheet: Download EPC16QI100N
- Chipdatas Part: CD87-EPC16QI100N
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/03 07:54 +0800
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