Description

Electronic Component Model: GT-48310A-B-2 is a high performance synchronous SRAM with a 2-bit burst address counter. It was originally developed for Level 2 Cache applications supporting high performance CPUs, but now it finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Specifications and features

• FT pin for user-configurable flow through or pipelined operation
• Dual Cycle Deselect (DCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available

Application Scenarios

This electronic component model is commonly used in various applications including DSP main store and networking chip set support.

Comparison

- High performance synchronous SRAM

- User-configurable flow through or pipelined operation

- Dual Cycle Deselect (DCD) operation

- Low power consumption with automatic power-down for portable applications

- Limited to synchronous SRAM applications

- Only available in 100-lead TQFP package