Description

The ADSP-TS101SAB1Z-100 is a TigerSHARC® processor designed for large signal processing tasks and communications infrastructure in demanding multiprocessor DSP applications. With a static superscalar architecture and very wide memory widths, this DSP provides exceptional performance and supports 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing. The TigerSHARC processor can execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.

Specifications and features

• 300 MHz, 3.3 ns instruction cycle rate
• 6M bits of internal—on-chip—SRAM memory
• 19 mm × 19 mm (484-ball) or 27 mm × 27 mm (625-ball) PBGA package
• Dual computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
• Dual integer ALUs, providing data addressing and pointer manipulation
• Integrated I/O includes 14-channel DMA controller, external port, 4 link ports, SDRAM controller, programmable flag pins, 2 timers, and timer expired pin for system integration
• 1149.1 IEEE compliant JTAG test access port for on-chip emulation
• On-chip arbitration for glueless multiprocessing with up to 8 TigerSHARC processors on a bus

Application Scenarios

The ADSP-TS101SAB1Z-100 is ideal for use in telecommunications infrastructure and other large multiprocessor DSP applications. It also supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, other DSPs (multiprocessor), and host processors, making it a flexible choice for a variety of applications.

Comparison

• Optimized for large signal processing tasks and communications infrastructure
• Exceptional performance on DSP algorithms and I/O benchmarks
• Flexible instruction set and high-level language-friendly DSP architecture make it easier to program
• Supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, other DSPs (multiprocessor), and host processors
• Enables scalable multiprocessing systems with low communications overhead

• None identified