LCMXO1200C-3MN132C - Brand New Lattice Semiconductor Programmable Logic Device (CPLDs/FPGAs)
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Description
The LCMXO1200C-3MN132C is a programmable logic device (CPLD/FPGA) designed to meet the requirements of applications typically addressed by CPLDs and low-capacity FPGAs, including glue logic, bus bridging, bus interfacing, power-up control, and control logic. It offers a non-volatile, infinitely reconfigurable design with excellent design security and no bit stream to intercept. Additionally, the LCMXO1200C-3MN132C comes with sleep mode, TransFR reconfiguration (TFR), flexible I/O buffer, and system-level support.
Specifications and Features
- Non-volatile, infinitely reconfigurable design
- Instant-on – powers up in microseconds
- Single chip, no external configuration memory required
- Design security with no bit stream to intercept
- Reconfigure SRAM based logic in milliseconds
- SRAM and non-volatile memory programmable through JTAG port
- Supports background programming of non-volatile memory
- Sleep mode allows up to 100x static current reduction
- In-field logic update while system operates with TransFR reconfiguration (TFR)
- High I/O to Logic Density with 256 to 2280 LUT4s and 73 to 271 I/Os with extensive package options
- Density migration supported with lead-free/RoHS compliant packaging
- Embedded and Distributed Memory with up to 27.6 Kbits sysMEM Embedded Block RAM, up to 7.5 Kbits distributed RAM, and dedicated FIFO control logic
- Flexible I/O Buffer with programmable sysIO buffer supporting a wide range of interfaces, such as LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, and RSDS
- sysCLOCK PLLs with up to two analog PLLs per device, clock multiply, divide, and phase shifting
- System-level support with IEEE Standard 1149.1 Boundary Scan, onboard oscillator, devices operating with 3.3V, 2.5V, 1.8V, or 1.2V power supply, and IEEE 1532 compliant in-system programming
Application Scenarios
The LCMXO1200C-3MN132C can be applied to various fields that require low-capacity FPGAs and CPLDs, such as glue logic, bus bridging, bus interfacing, power-up control, and control logic.
Comparison
Advantages- Non-volatile, infinitely reconfigurable design
- Instant-on – powers up in microseconds
- Density migration supported with lead-free/RoHS compliant packaging
- Flexible I/O buffer with programmable sysIO buffer supporting a wide range of interfaces
- System-level support with IEEE Standard 1149.1 Boundary Scan, onboard oscillator, devices operating with 3.3V, 2.5V, 1.8V, or 1.2V power supply, and IEEE 1532 compliant in-system programming
Disadvantages- Not suitable for applications requiring high capacity FPGAs
- Limited memory capacity compared to high-capacity FPGAs
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Datasheet
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Shopping guide
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- Datasheet: Download LCMXO1200C-3MN132C
- Chipdatas Part: CD86-LCMXO1200C-3MN132C
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/13 20:41 +0800
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