EPM3032AT - Brand New Intel / Altera Programmable Logic Device (CPLDs/FPGAs)
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Description
Electronic Component Model: EPM3032AT is a programmable logic device (CPLD/FPGA) from the MAX 3000A series, designed based on the Altera MAX architecture. It operates with a 3.3-V supply voltage and provides 600 to 10,000 usable gates, with pin-to-pin delays as fast as 4.5 ns and counter speeds of up to 227.3 MHz. The device is compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.
Specifications and features
- High-performance, low-cost CMOS EEPROM-based programmable logic devices (PLDs) built on a MAX architecture
- 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability.
- Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990.
- Enhanced ISP features for faster programming, ensuring complete programming, and pull-up resistor on I/O pins during in-system programming.
- High-density PLDs ranging from 600 to 10,000 usable gates.
- 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz.
- MultiVolt I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels.
- Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J-lead chip carrier (PLCC), and FineLine BGA packages.
- Hot-socketing support.
- Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance.
- Industrial temperature range.
- PCI compatible.
- Bus-friendly architecture including programmable slew-rate control.
- Open-drain output option.
- Programmable macrocell flip-flops with individual clear, preset, clock, and clock enable controls.
- Programmable power-saving mode for a power reduction of over 50% in each macrocell.
- Configurable expander product-term distribution, allowing up to 32 product terms per macrocell.
- Programmable security bit for protection of proprietary designs.
- Enhanced architectural features, including 6 or 10 pin- or logic-driven output enable signals, two global clock signals with optional inversion, enhanced interconnect resources for improved routability, and programmable output slew-rate control.
- Software design support and automatic place-and-route provided by Altera's development systems for Windows-based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations.
- Additional design entry and simulation support provided by EDIF 200 and 300 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third-party manufacturers.
- Programming support with the Altera master programming unit (MPU), MasterBlaster communications cable, ByteBlasterMV parallel port download cable, BitBlaster serial download cable, and programming hardware from third-party manufacturers and any in-circuit tester that supports Jam Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf).
Application Scenarios
EPM3032AT can be used in various applications that require programmable logic devices with low cost, high performance, and compatibility with PCI specifications. Some example scenarios include:
- Industrial automation
- Embedded systems
- Communications equipment
- Data processing and storage systems
- Control systems
- Instrumentation
Comparison
Advantages- Low-cost and high-performance
- Compatible with PCI specifications
- 3.3-V in-system programmability
- Wide range of pin counts and package options
- Enhanced features for faster programming and power-saving
Disadvantages- Requires programming hardware for device programming
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Datasheet
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Shopping guide
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- Datasheet: Download EPM3032AT
- Chipdatas Part: CD94-EPM3032AT
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/13 09:09 +0800
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