Functional Description

The CY7C1334 is a 3.3V, 64K by 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write-Read transitions.The CY7C1334 is pin/functionally compatible to ZBT SRAM MT55L64L32P

Features

• Pin compatible and functionally equivalent to ZBT™ device MT55L64L32P
• Supports 133-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate the need to use OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write Capability
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
— 7.0 ns (for 80-MHz device)
— 10.0 ns (for 50-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP package
• Burst Capability—linear or interleaved burst order