ISPLSI5128VE-125LT128-100I - Brand New LATTICE IC Chips
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Description
The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.
Specifications and features
• SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 12000 PLD Gates / 256 Macrocells
— Up to 192 I/O Pins
— 256 Registers
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package Options
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single Level Global Routing Pool and SuperWide GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Slew and Skew Programmable I/O (SASPI/O™) Supports Programmable Bus Hold, Pull-up, Open Drain and Slew and Skew Rate Options
— Six Global Output Enable Terms, Two Global OE Pins and One Product Term OE per Macrocell
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
— PC and UNIX PlatformsApplication Scenarios
The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is commonly used in various electronic devices and systems that require high-density programmable logic. Some common application scenarios include:
- Industrial automation systems
- Communication equipment
- Automotive electronics
- Consumer electronics
- Medical devices
- Aerospace and defense systemsComparison
Advantages- SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC design
- Wide range of power supply options
- High-speed global interconnect
- Supports multiple input/output voltage levels
- Programmable speed/power logic path optimization
- In-system programmable for increased manufacturing yields
- Boundary scan testable for improved product quality
- Enhanced pin-locking architecture for better routing efficiency
- Multiple clock options and programmable I/O features
- Integrated with leading CAE vendors
Disadvantages- Limited maximum operating frequency of 125 MHz
- Propagation delay of 7.5 ns
- Limited number of macrocells and registers compared to some other models
- Limited package options -
Similar parts: 430483 , Click to view
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Datasheet
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Shopping guide
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- Datasheet: Download ISPLSI5128VE-125LT128-100I
- Chipdatas Part: CD87-ISPLSI5128VE-125LT128-100I
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/10/01 18:52 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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