Description

The PEF20534H-10 is a DMA Supported Serial Communication Controller with four independent serial channels. It provides a large set of protocol support and variety in serial interface configuration, allowing easy integration to different environments and applications.

Specifications and Features

• Serial Communication Controllers (SCCs)
• Four independent channels
• Full duplex data rates on each channel of up to 10 Mbit/s sync - 2 Mbit/s with DPLL, 2 Mbit/s async
• Full duplex data rate of up to 52 Mbit/s on any two channels in high speed mode (HDLC: Address Mode 0 and extended transparent protocol mode); up to 45 Mbit/s on any two channels in high speed mode (HDLC: PPP modes). The aggregate bandwidth for all channels is limited to 108 Mbit/s per direction.
• 17 DWORDs deep receive FIFO per SCC (+ 128 DWORDs central receive FIFO)
• 8 DWORDs deep transmit FIFO per SCC (+ 128 DWORDs central transmit FIFO)
• On-chip clock generation or external clock sources
• On-chip DPLLs for clock recovery
• Baud rate generator
• Clock gating signals
• Clock gapping capability
• Programmable time-slot capability for connection to TDM interfaces (e.g. T1, E1)
• NRZ, NRZI, FM and Manchester data encoding
• Optional data flow control using modem control lines (RTS, CTS, CD)
• Support of bus configuration by collision detection and resolution

Application Scenarios

The PEF20534H-10 Serial Communication Controller is designed for various applications including but not limited to:

• Data communication systems
• Networking equipment
• Industrial automation
• Telecommunication devices

Comparison

• Four independent serial channels for versatile communication
• High data rates for efficient data transmission
• Large FIFOs for improved buffer management
• Flexible clocking options for different applications
• Support for various data encoding schemes

• Not suitable for low-speed applications
• Requires external clock source for specific configurations