Description

This is a family of 1048576-word by 4-bit dynamic RAMs, fabricated with the high performance CMOS process,and is ideal for largecapacity memory systems where high speed, low power dissipation, and low costs are essential.
The use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities.
Self or extended refresh current is low enough for battery back-up application.

Specifications and features

● Standard 26 pin SOJ, 26 pin TSOP(II)
● Single 5V±10%supply
● Low stand-by power dissipation
CMOS lnput level - - - - - - - - - - - - - 5.5mW (Max)
CMOS lnput level - - - - - - - - - - - - - 550µW (Max)
● Low operating power dissipation
M5M44405Cxx-5,-5S - - - - - - - - - - - 687.5mW (Max)
M5M44405Cxx-6,-6S - - - - - - - - - - - 550.0mW (Max)
M5M44405Cxx-7,-7S - - - - - - - - - - - 467.5mW (Max)
● Self refresh capabiility
Self refresh current - - - - - - - - - - - - - - - 120µA(max)
● Extended refresh capability
Extended refresh current - - - - - - - - - - - 120µA(max)
● Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-5S,-6S,-7S) capabilities
● Early-write mode and OE and W to control output buffer impedance
● All inputs, output TTL compatible and low capacitance
● 1024 refresh cycles every 16.4ms (A0~A9)
● 1024refresh cycle every 128ms (A0~A9)
● 4-bit parallel test mode capability
* : Applicable to self refresh version (M5M44405CJ,TP-5S,-6S,-7S : option) only

Application Scenarios

Main memory unit for computers, Microcomputer memory, Refresh memory for CRT, Frame Buffer memory for CRT

Comparison