MC100EP196FA - Brand New ON Semiconductor Delay Lines
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Description
The MC100EP196FA is a programmable delay chip (PDC) designed for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. With a maximum input clock frequency of over 1.2 GHz, it offers a programmable range of 0 ns to 10 ns and a delay range of 2.2 ns to 12.2 ns. The MC100EP196FA operates in both PECL and NECL modes, with the PECL mode operating range from VCC = 3.0 V to 3.6 V and VEE = 0 V, and the NECL mode operating range from VCC = 0 V and VEE = -3.0 V to -3.6 V. It has an open input default state, safety clamp on inputs, and accepts ECL, LVCMOS, or LVTTL inputs. The MC100EP196FA also features a VBB output reference voltage and is available in Pb-Free packages.Specifications and features
• Maximum Input Clock Frequency: >1.2 GHz Typical
• Programmable Range: 0 ns to 10 ns
• Delay Range: 2.2 ns to 12.2 ns
• 10 ps Increments
• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
• Open Input Default State
• Safety Clamp on Inputs
• A Logic High on the EN Pin Will Force Q to Logic Low
• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
• VBB Output Reference Voltage
• Pb-Free Packages are Available
Application Scenarios
The MC100EP196FA is commonly used in applications that require clock deskewing and timing adjustment. It is particularly useful in systems where precise timing is critical, such as high-speed data transmission, telecommunications, and signal processing.
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- Datasheet: Download MC100EP196FA
- Chipdatas Part: CD90-MC100EP196FA
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
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- Last Updated: 2024/06/03 04:36 +0800
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