**The DSP56311 is intended for applications requiring a large amount of

on-chip memory, such as networking and wireless infrastructure applications. The EFCOP can accelerate general filtering applications, such as echo- cancellation applications, correlation, and general-purpose convolution-based algorithms.**

The Motorola DSP56311, a member of the DSP56300 Digital Signal Processor (DSP) family, supports network applications with general filtering operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.

DSP56311 Features

High-Performance DSP56300 Core
• 150 million instructions per second (MIPS) (270 MIPS using the EFCOP in filtering applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control
• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals
• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and output clock with skew elimination
• Hardware debugging support including On-Chip Emulation (OnCE) module, Joint Test Action Group (JTAG) Test Access Port (TAP)

Enhanced Filtering Coprocessor (EFCOP)

• On-chip 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 150 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
— Real Finite Impulse Response (FIR) with real taps
— Complex FIR with complex taps
— Complex FIR generating pure real or pure imaginary outputs alternately
— A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
— Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
— Direct form 2 (DFII) IIR filter
— Four scaling factors (1, 4, 8, 16) for IIR output
— Adaptive FIR filter with true least mean square (LMS) coefficient updates
— Adaptive FIR filter with delayed LMS coefficient updates

On-Chip Peripherals

• Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled

On-Chip Memories

• 192 × 24-bit bootstrap ROM
• 128 K RAM total
• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:

Off-Chip Memory Expansion

• Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address lines
• Program memory expansion to one 256 K × 24-bit words memory space using the standard external address lines
• External memory expansion port
• Chip Select Logic for glueless interface to static random access memory (SRAMs)
• On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs) up to 100 MHz operating frequency

Reduced Power Dissipation

• Very low-power CMOS design
• Wait and Stop low-power standby modes
• Fully static design specified to operate down to 0 Hz (dc)
• Optimized power management circuitry (instruction-dependent, peripheral- dependent, and mode-dependent)

Packaging

The DSP56311 is available in a 196-pin MAP-BGA package.

Target Applications

• Wireless and wireline infrastructure applications
• Multi-channel wireless local loop systems
• DSP resource boards
• High-speed modem banks
• Packet telephony