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INTRODUCTION
Unless specifically noted, all references to the 80C186EC apply to the 80C188EC, 80L186EC, and 80L188EC. References to pins that differ between the 80C186EC/80L186EC and the 80C188EC/80L188EC are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physically and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical.
■ Fully Static Operation
■ True CMOS Inputs and Outputs
■ Integrated Feature Set:
— Low-Power, Static, Enhanced 8086 CPU Core
— Two Independent DMA Supported UARTs, each with an Integral Baud Rate Generator
— Four Independent DMA Channels
— 22 Multiplexed I/O Port Pins
— Two 8259A Compatible Programmable Interrupt Controllers
— Three Programmable 16-Bit Timer/Counters
— 32-Bit Watchdog Timer
— Ten Programmable Chip Selects with Integral Wait-State Generator
— Memory Refresh Control Unit
— Power Management Unit
— On-Chip Oscillator
— System Level Testing Support (ONCE Mode)
■ Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O
■ Low-Power Operating Modes:
— Idle Mode Freezes CPU Clocks but Keeps Peripherals Active
— Powerdown Mode Freezes All Internal Clocks
— Powersave Mode Divides All Clocks by Programmable Prescalar
■ Available in Extended Temperature Range (-40°C to +85°C)
■ Supports 80C187 Numerics Processor Extension (80C186EC only)
■ Package Types:
— 100-Pin EIAJ Quad Flat Pack (QFP)
— 100-Pin Plastic Quad Flat Pack (PQFP)
— 100-Pin Shrink Quad Flat Pack (SQFP)
■ Speed Versions Available (5V):
— 25 MHz (80C186EC25/80C188EC25)
— 20 MHz (80C186EC20/80C188EC20)
— 13 MHz (80C186EC13/80C188EC13)
■ Speed Version Available (3V):
— 16 MHz (80L186EC16/80L188EC16)
— 13 MHz (80L186EC13/80L188EC13) -
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