Description

The LatticeECP/EC family of FPGA devices has been optimized to deliver mainstream FPGA features at low cost. For maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-DSP (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™ (EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function blocks to achieve lower cost solutions.

Specifications and Features

• Extensive Density and Package Options
• 1.5K to 41K LUT4s
• 65 to 576 I/Os
• Density migration supported
• sysDSP™ Block (LatticeECP™ Versions)
• High performance multiply and accumulate
• 4 to 10 blocks
• Embedded and Distributed Memory
• 18 Kbits to 645 Kbits sysMEM™ Embedded Block RAM (EBR)
• Up to 163 Kbits distributed RAM
• Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide range of interfaces:
• LVCMOS 3.3/2.5/1.8/1.5/1.2
• LVTTL
• SSTL 3/2 Class I, II, SSTL18 Class I
• HSTL 18 Class I, II, III, HSTL15 Class I, III
• PCI
• LVDS, Bus-LVDS, LVPECL, RSDS
• Dedicated DDR Memory Support
• Implements interface up to DDR400 (200MHz)
• sysCLOCK™ PLLs
• Up to 4 analog PLLs per device
• Clock multiply, divide and phase shifting
• System Level Support
• IEEE Standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability
• SPI boot flash interface
• 1.2V power supply
• Low Cost FPGA
• Features optimized for mainstream applications
• Low cost TQFP and PQFP packaging

Application Scenarios

This model is suitable for a wide range of applications, including but not limited to:

• Mainstream FPGA applications
• Low cost solutions
• DSP-intensive applications

Comparison

• Optimized for mainstream FPGA applications
• Low cost solutions
• Provides high-performance DSP blocks on-chip
• Supports extensive density and package options
• Flexible I/O buffer supports a wide range of interfaces

• Not suitable for high-performance or specialized applications
• Limited DDR memory support
• Lower density compared to other FPGA models