Description

Electronic Component Model: QG6321SL97Q is a third-generation flash FPGA from the ProASIC3E family by Microsemi. It offers superior performance, density, and features compared to the ProASICPLUS family. With nonvolatile flash technology, it provides the advantages of being secure, low power, and a single-chip solution that is Instant On. It is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. This model enables designers to create high-density systems using existing ASIC or FPGA design flows and tools.

Specifications and features

• High Capacity: 600k to 3 Million System Gates
• 108 to 504kbits of True Dual-Port SRAM
• Up to 620 User I/Os
• Reprogrammable Flash Technology: 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• On-Chip User Nonvolatile Memory: 1kbit of FlashROM with Synchronous Interfacing
• High Performance: 350 MHz System Performance, 3.3V, 66 MHz 64-Bit PCI
• In-System Programming (ISP) and Security:
  • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
  • FlashLock Designed to Secure FPGA Contents
• Low Power:
  • Core Voltage for Low Power
  • Support for 1.5-V-Only Systems
  • Low-Impedance Flash Switches
• High-Performance Routing Hierarchy:
  • Segmented, Hierarchical Routing and Clock Structure
  • Ultra-Fast Local and Long-Line Network
  • Enhanced High-Speed, Very-Long-Line Network
  • High-Performance, Low-Skew Global Network
  • Architecture Supports Ultra-High Utilization
• Pro (Professional) I/O:
  • 700 Mbps DDR, LVDS-Capable I/Os
  • 1.5V, 1.8V, 2.5V, and 3.3V Mixed-Voltage Operation
  • Bank-Selectable I/O Voltages—up to 8 Banks per Chip
  • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V / 2.5V / 1.8V / 1.5V, 3.3V PCI / 3.3V PCI-X, and LVCMOS 2.5V / 5.0V Input
  • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS
  • Voltage-Referenced I/O Standards: GTL+ 2.5V / 3.3V, GTL 2.5V / 3.3V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II
  • I/O Registers on Input, Output, and Enable Paths
  • Hot-Swappable and Cold Sparing I/Os
  • Programmable Output Slew Rate and Drive Strength
  • Programmable Input Delay
  • Schmitt Trigger Option on Single-Ended Inputs
  • Weak Pull-Up/-Down
  • IEEE 1149.1 (JTAG) Boundary Scan Test
  • Pin-Compatible Packages across the ProASIC3E Family
• Clock Conditioning Circuit (CCC) and PLL:
  • Six CCC Blocks, Each with an Integrated PLL
  • Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
  • Wide Input Frequency Range (1.5 MHz to 350 MHz)
• SRAMs and FIFOs:
  • Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
  • True Dual-Port SRAM (except ×18)
  • 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz
• ARM Processor Support in ProASIC3E FPGAs:
  • M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available with or without Debug

Application Scenarios

This electronic component model can be used in a wide range of applications, including but not limited to:

• ASIC and FPGA design flows
• High-density system development
• Electronics prototyping
• Embedded systems

Comparison

• High capacity and performance
• Reprogrammable and Instant On
• Secure and low power
• Support for various I/O standards and voltages
• Wide range of operating frequencies
• ARM processor support

• May require familiarity with specific design flows and tools
• Not suitable for all types of electronic systems