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Description
The PM7366-BI is a monolithic integrated circuit that serves as a frame engine and datalink manager, implementing HDLC processing and PCI Bus memory management functions. It supports a maximum of 128 bi-directional channels.
Specifications and Features
- Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller.
- Supports up to 128 bi-directional HDLC channels assigned to a maximum of 8 channelised T1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for E1).
- Supports up to 8 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link; subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 can have a clock rate of up 52 MHz when SYSCLK is at 33 MHz. Channels assigned to links 3 to 7 can have a clock rate of up to 10 MHz.
- Supports up to two bi-directional HDLC Channels each assigned to an unchannelised arbitrary rate link of up to 52 MHz when SYSCLK is at 33 MHz.
- Supports a mix of up to 8 channelised and unchannelised links; subject to the constraint of a maximum of 128 channels and a maximum aggregate link clock rate of 64 MHz in each direction.
- For each channel, the HDLC receiver performs flag sequence detection, bit de-stuffing, and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences. The receiver also checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length.
- Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots.
- For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.
- For each channel, the HDLC transmitter performs flag sequence generation, bit stuffing, and, optionally, frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows.
- Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted.
- Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots.
- Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/gather capabilities.
- Provides 8 kbytes of on-chip memory for partial packet buffering in each direction. This memory can be configured to support a variety of different channel configurations from a single channel with 8 kbytes of buffering to 128 channels, each with a minimum of 48 bytes of buffering.
- Supports PCI burst sizes of up to 128 bytes for transfers of packet data.
- Pin compatible with PM7364 (FREEDM-32) device.
- Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
- Supports 3.3 and 5 Volt PCI signaling environments.
- Low power CMOS technology.
- Available in 256 pin enhanced ball grid array (SBGA) or 272 pin plastic ball grid array (PBGA) packages (27 mm X 27 mm).Application Scenarios
- IETF PPP interfaces for routers.
- Frame Relay interfaces for ATM or Frame Relay switches and multiplexors.
- FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexors.
- D-channel processing in ISDN terminals and switches.
- Internet/Intranet access equipment.
- Packet-based DSLAM equipment.Comparison
Advantages- Single-chip design for convenient integration.
- Supports a wide range of HDLC channels, both channelised and unchannelised.
- High-speed performance with a maximum aggregate link clock rate of 64 MHz.
- Flexible configuration options for different channel setups.
- Supports multiple frame check sequence validation methods.
- Provides on-chip memory for partial packet buffering.
- Pin compatible with PM7364 (FREEDM-32) device, allowing for easy replacement.
- Supports a variety of signaling environments.
- Low power consumption.Disadvantages- No specific disadvantages identified. -
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- Datasheet: Download PM7366-BI
- Chipdatas Part: CD87-PM7366-BI
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
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- Last Updated: 2024/10/01 12:05 +0800
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