Description

This document contains the specifications for the Intel® Advanced+ Boot Block Flash Memory (C3) Stacked Chip Scale Package (SCSP) device. C3 SCSP memory solutions are offered in the following combinations:
• 32-Mbit flash + 8-Mbit SRAM
• 32-Mbit flash + 4-Mbit SRAM
• 16-Mbit flash + 4-Mbit SRAM
• 16-Mbit flash memory + 2-Mbit SRAM
The C3 SCSP device combines flash memory and SRAM into a single package, which provides secure low-voltage memory solutions for portable applications. The flash memory provides enhanced security, instant locking/unlocking of any flash block with zero-latency, a 128-bit protection register that enables unique device identification to meet the needs of next-generation portable applications, and improved 12 V production programming for increased factory throughput.

Specifications and features

■ Flash Memory Plus SRAM
—The device reduces memory board space required and simplifies PCB design complexity.
■ SCSP Technology
—Smallest memory subsystem footprint, with an area of 8 x 10 mm for 16 Mbit (0.13 µm) Flash + 2 Mbit or 4 Mbit SRAM and an area of 8 x 12 mm for 32 Mbit (0.13 µm) Flash + 4 Mbit or 8 Mbit SRAM. The height is 1.20 mm for 16 Mbit (0.13 µm) Flash + 2 Mbit or 4 Mbit SRAM, and 32 Mbit (0.13 µm) Flash + 8 Mbit SRAM, and 1.40 mm for 32 Mbit (0.13 µm) Flash + 4 Mbit SRAM. This family also includes 0.25 µm, 0.18 µm, and 0.13 µm technologies.
■ Advanced SRAM Technology
—70 ns access time, low power operation, and low voltage data retention mode.
■ Intel® Flash Data Integrator (FDI) Software
—Real-time data storage and code execution in the same memory device, and full flash file manager capability.
■ Advanced+ Boot Block Flash Memory
—70 ns access time, instant individual block locking, 128-bit protection register, 12 V production programming, fast program and erase suspend, extended temperature -25 °C to +85 °C.
■ Blocking Architecture
—Block sizes for code + data storage, 4-Kword parameter blocks, 64-Kbyte main blocks, and 100,000 erase cycles per block.
■ Low Power Operation
—Asynchronous read current: 9 mA (Flash), standby current: 7 µA (Flash), and automatic power saving mode.
■ Flash Technologies
—0.25 µm ETOX™ VI, 0.18 µm ETOX™ VII, and 0.13 µm ETOX™ VIII Flash Technologies.

Application Scenarios

The Intel® Advanced+ Boot Block Flash Memory (C3) Stacked Chip Scale Package (SCSP) device is suitable for various portable application scenarios where secure low-voltage memory solutions are required. It can be used in devices such as smartphones, tablets, portable media players, and other similar portable electronic devices.

Comparison

• Combines flash memory and SRAM into a single package, reducing memory board space and simplifying PCB design complexity.
• Enhanced security with instant locking/unlocking of any flash block with zero-latency.
• 128-bit protection register enables unique device identification for next-generation portable applications.
• Improved 12 V production programming for increased factory throughput.
• Smallest memory subsystem footprint with various options available.
• Advanced SRAM technology offers low access time, low power operation, and low voltage data retention mode.
• Intel® Flash Data Integrator (FDI) Software provides real-time data storage and code execution in the same memory device.
• Advanced+ Boot Block Flash Memory with various features such as individual block locking, 128-bit protection register, and 12 V production programming.
• Blocking architecture with various block sizes for code + data storage and high erase cycle per block.
• Low power operation with asynchronous read current and automatic power saving mode.
• Utilizes advanced flash technologies for optimal performance.

• No specific disadvantages were mentioned in the provided information.