Description

PMC-Sierra’s RM7000-266T is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit. To keep its multiple execution units running efficiently, the RM7000-266T integrates 16 KB 4-way set associative instruction and data caches, backed up by an integrated 256 KB 4-way set associative secondary cache. An optional external tertiary cache provides high-performance capability even in applications with very large data sets. The RM7000-266T is ideally suited for high-end embedded control applications such as internetworking, high-performance image manipulation, high-speed printing, and 3-D visualization. It is also applicable to the low-end workstation market where its balanced integer and floating-point performance, and direct support for a large tertiary cache (up to 8 MB), provide outstanding price/performance.

Specifications and features

• Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance
• Operating frequency: 200, 250, 266, 300 MHz
• >500 Dhrystone 2.1 MIPS @ 300 MHz
• High-performance system interface
• 1000 MB per second peak throughput
• 125 MHz max. freq., multiplexed address/data
• Supports two outstanding reads with out-of-order return
• Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
• Integrated primary and secondary caches — all are 4-way set associative with 32 byte line size
• 16 KB instruction, 16 KB data, 256 KB on-chip secondary cache
• Per line cache locking in primaries and secondary
• Fast Packet Cache™ increases system efficiency in networking applications
• Integrated external cache controller (up to 8 MB)
• High-performance floating-point unit — 600 MFLOPS maximum
• Single cycle repeat rate for common single-precision operations and some double-precision operations
• Single cycle repeat rate for single-precision combined multiply-add operations
• Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations
• MIPS IV Superset Instruction Set Architecture
• Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
• Single-cycle floating-point multiply-add
• Integrated memory management unit
• Fully associative joint TLB (shared by I and D translations)
• 64/48 dual entries map 128/96 pages
• Variable page size
• Embedded application enhancements
• Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and three operand multiply instruction (MUL)
• I&D Test/Break-point (Watch) registers for emulation & debug
• Performance counter for system and software tuning & debug
• Fourteen fully prioritized vectored interrupts - 10 external, 2 internal, 2 software
• Fully static CMOS design with dynamic power down logic
• RM5271 pin compatible, 304 pin TBGA package, 31x31 mm

Application Scenarios

The RM7000-266T microprocessor is widely used in high-end embedded control applications such as internetworking, high-performance image manipulation, high-speed printing, and 3-D visualization. It is also utilized in the low-end workstation market due to its balanced integer and floating-point performance and direct support for a large tertiary cache.

Comparison

• Highly integrated superscalar microprocessor
• Capable of issuing two instructions each processor cycle
• High-performance 64-bit integer units
• High-throughput, fully pipelined 64-bit floating point unit
• 16 KB 4-way set associative instruction and data caches
• Integrated 256 KB 4-way set associative secondary cache
• Optional external tertiary cache for high-performance capability
• Ideal for high-end embedded control applications
• Direct support for a large tertiary cache (up to 8 MB)
• Outstanding price/performance ratio

• Operating frequency options limited to 200, 250, 266, and 300 MHz
• Not suitable for applications with higher operating frequency requirements
• No support for larger external caches beyond 8 MB