Description

SAK-C167SR-LMGA-T is a high-performance 16-bit CPU with a 4-stage pipeline. It has a fast instruction cycle time of 80/60 ns at a CPU clock of 25/33 MHz. The CPU also features enhanced Boolean bit manipulation facilities and additional instructions to support high-level languages (HLL) and operating systems. With a register-based design and multiple variable register banks, it enables efficient context switching. The chip offers a total linear address space of 16 Mbytes for code and data, along with a 1024-byte on-chip special function register area.

Specifications and features

• High Performance 16-bit CPU with 4-Stage Pipeline
• 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock
• 400/303 ns Multiplication (16 × 16 bits), 800/606 ns Division (32 / 16 bits)
• Enhanced Boolean Bit Manipulation Facilities
• Additional Instructions to Support HLL and Operating Systems
• Register-Based Design with Multiple Variable Register Banks
• Single-Cycle Context Switching Support
• 16 Mbytes Total Linear Address Space for Code and Data
• 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input
• On-Chip Memory Modules
• 2 Kbytes On-Chip Internal RAM (IRAM)
• 2 Kbytes On-Chip Extension RAM (XRAM)
• 128/32 Kbytes On-Chip Mask ROM
• On-Chip Peripheral Modules
• 16-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 µs
• Two 16-Channel Capture/Compare Units
• 4-Channel PWM Unit
• Two Multi-Functional General Purpose Timer Units with 5 Timers
• Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
• On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects (Full CAN / Basic CAN)
• Up to 16 Mbytes External Address Space for Code and Data
• Programmable External Bus Characteristics for Different Address Ranges
• Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width
• Five Programmable Chip-Select Signals
• Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle and Power Down Modes
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 144-Pin MQFP Package
• 176-Pin BGA Package1)

Application Scenarios

The SAK-C167SR-LMGA-T is suitable for various applications in the field of IC Chips. It can be used in automotive electronics, industrial control systems, communication equipment, and many other electronic devices that require high-performance computing capabilities.

Comparison

- High-performance 16-bit CPU with a 4-stage pipeline

- Fast instruction cycle time

- Enhanced Boolean bit manipulation facilities

- Additional instructions to support HLL and operating systems

- Register-based design with multiple variable register banks

- Single-cycle context switching support

- Large linear address space for code and data

- On-chip special function register area

- Versatile on-chip peripheral modules

- Limited external address space

- Limited number of I/O lines

- Complex bus arbitration mechanism