74ALVC162836ADGG - Brand New PHI Universal Bus Function
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DESCRIPTION
The 74ALVC162836A is an 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).
When LE is HIGH, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.FEATURES
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 12 mA at 3.0 V
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Output drive capability 50 Ω transmission lines @ 85°C
• Integrated 30 Ω termination resistors
• Diode clamps to VCC and GND on all inputs
• Input diodes to accommodate strong drivers -
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
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DHL, FedEx, EMS, SF Express, and Registered Air MailShipping tracking:
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Popular parts of the same kind
- Datasheet: Download 74ALVC162836ADGG
- Chipdatas Part: CD91-74ALVC162836ADGG
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/03 03:19 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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The fee is charged according to the rule of PayPal.
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Western Union charge US$0.00 banking fee.
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We recommend to use bank transfer for large orders to save on handling fees.
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