Description

The RTL8196B-GR is an integrated System-on-a-Chip (SoC) Application Specific Integrated Circuit (ASIC) that implements a basic L2 5-port Ethernet switch and a high performance CPU. The embedded RISC CPU is an RLX4181, and the clock rate can be up to 400MHz. To improve computational performance, a 16-Kbyte I-Cache, 8-Kbyte D-Cache, 16-K I-MEM, and 8-Kbyte D-MEM are provided. A standard 5-signal P1149.1 compliant EJTAG test interface is supported for CPU testing and software development.

Specifications and features

This electronic component model is packed with the following specifications and features:

• - Embedded RISC CPU, RLX4181 with 16K I-Cache, 8K D-Cache, 16K I-MEM, 8K D-MEM
• - Supports MIPS-1 ISA, MIPS16 ISA
• - Clock rate up to 400MHz
• - Provides a standard 5-signal P1149.1 EJTAG test port
• - Supports RLX4181 CPU suspend mode
• - Five Ethernet MAC integrated switch with five 10M/100Mbps physical layers and transceivers for IEEE 802.3 10Base-T and 100Base-TX
• - Non-blocking wire-speed reception and transmission and non-head-of-line blocking/forwarding
• - Internal 512Kbit SRAM for packet buffering
• - Internal 1024 entry 4-way hash L2 look up table
• - Supports source and destination MAC address filtering
• - Supports IEEE 802.1x port-based and MAC-based Network Access Control
• - Complies with IEEE 802.3/802.3u/802.1q/802.1d
• - Flexible full-duplex 802.3x flow control and optional half-duplex backpressure flow control
• - MAC learning supports Shared VLAN Learning (SVL) and Independent VLAN Learning (IVL) modes
• - Supports BSD mbuf-like packet structure with adjustable cluster size (128-byte to 2Kbyte) to provide optimum memory utilization
• - Provides the ‘To-CPU reason’ in the packet header to facilitate packet processing
• - The NIC DMA supports multiple descriptor-ring architecture for QoS applications (supports 6 RX descriptor rings and 2 TX descriptor rings)
• - Supports one PCI Express Host with integrated PHY
• - Supports one 16550 UART
• - Supports up to 17 GPIO pins
• - Supports one-port USB 2.0 host interface
• - Embedded USB PHY
• - Supports two Flash banks that can be configured as 8/16-bit bus, 256k/512k/1M/2M/4M/8M bytes
• - System supports up to 16Mbyte Flash memory space
• - Boot up from NOR Flash is supported
• - Supports 4 channels for SPI Flash application
• - Boot up from SPI Flash is supported
• - System supports up to 32Mbyte Flash memory space
• - Supports two SDRAM banks that can be configured as 2M/4M/8M/16M/32M/64Mbyte
• - 16-bit SDRAM data bus is supported
• - System totally supports up to 128Mbyte SDRAM memory space
• - Supports Green Ethernet
• - Cable length power saving
• - Power down power saving
• - Supports IEEE 802.3az Draft 2.0 Energy Efficient Ethernet (EEE) for 100Base-TX in full duplex operation, and 10Base-T in full/half duplex mode
• - Supports Link down power saving in Ethernet PHY
• - Supports two hardware timers and one watchdog timer
• - Per-port configurable auto-crossover function
• - Single 25MHz crystal or 40MHz clock input
• - PQFP 128-pin package

Application Scenarios

The RTL8196B-GR electronic component model is commonly used in applications such as:

• - Network switches
• - Routers
• - Ethernet hubs
• - Embedded systems
• - Industrial automation

Comparison

- Integrated System-on-a-Chip (SoC) design for efficient performance

- High-performance CPU with clock rate up to 400MHz

- Provides a standard 5-signal P1149.1 compliant EJTAG test interface for CPU testing and software development

- Supports multiple descriptor-ring architecture for Quality of Service (QoS) applications

- Supports various memory interfaces including Flash, SDRAM, and USB

- Supports Green Ethernet for power-saving

- Per-port configurable auto-crossover function for easy network setup

- Limited GPIO pins (up to 17)

- Limited UART support (one 16550 UART)

- Limited Flash memory space (up to 32Mbyte)

- Limited SDRAM memory space (up to 128Mbyte)

- PQFP 128-pin package may be less suitable for space-constrained designs