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MC100EP195FAG - Brand New onsemi Delay Lines - Datasheet - Chipdatas
MC100EP195FAG
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MC100EP195FAG - Brand New onsemi Delay Lines

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Brand:onsemi
Category:Delay Lines
Chipdatas Part No.:CD87-MC100EP195FAG
Manufacturer Part No.:MC100EP195FAG
Datecode:09+
Package:32-LQFP
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  • Description

    The MC100EP195FAG is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It belongs to the 100 Series and contains temperature compensation. The maximum input clock frequency is greater than 1.2 GHz, with a typical programmable range of 0 ns to 10 ns and a delay range of 2.2 ns to 12.2 ns in 10 ps increments. It operates in PECL mode with a voltage range of VCC = 3.0 V to 3.6 V with VEE = 0 V, or in NECL mode with a voltage range of VCC = 0 V with VEE = -3.0 V to -3.6 V. It has an open input default state and a safety clamp on inputs. The EN pin can be set to logic high to force Q to logic low. D[10:0] can accept either ECL, LVCMOS, or LVTTL inputs. It also features a VBB output reference voltage and is a Pb-Free device.

    Specifications and features

    • Product Category: Delay Lines
    • Programmable Delay Chip (PDC)
    • Variable delay of a differential NECL/PECL input transition
    • Belongs to the 100 Series with temperature compensation
    • Maximum input clock frequency: > 1.2 GHz Typical
    • Programmable Range: 0 ns to 10 ns
    • Delay Range: 2.2 ns to 12.2 ns
    • 10 ps Increments
    • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
    • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • A Logic High on the EN Pin Will Force Q to Logic Low
    • D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
    • VBB Output Reference Voltage
    • Pb-Free Device

    Application Scenarios

    The MC100EP195FAG Programmable Delay Chip (PDC) can be used in various applications, including clock deskewing, timing adjustment, and any other application that requires variable delay of a differential NECL/PECL input transition. It is suitable for both PECL and NECL mode operating ranges, and can accept different input types such as ECL, LVCMOS, or LVTTL. Its programmable and variable delay range makes it versatile for different scenarios.

    Comparison

    Advantages
    • Programmable delay range from 0 ns to 10 ns
    • Wide operating voltage range for both PECL and NECL mode
    • Supports different input types: ECL, LVCMOS, or LVTTL
    • Temperature compensation in the 100 Series
    • High maximum input clock frequency of > 1.2 GHz
    • Pb-Free device
    Disadvantages
    • None identified
  • Similar parts: 229 , Click to view
    Attributes Value
    Category Delay Lines
    Manufacturer onsemi
    Product Category Clock/Timing - Delay Lines
    Series 100EP
    Packaging Tray Alternate Packaging
    Unit-Weight 0.027302 oz
    Mounting-Style SMD/SMT
    Package-Case LQFP-32
    Operating-Temperature -40°C ~ 85°C
    Mounting-Type Surface Mount
    Function Programmable
    Voltage-Supply 3 V ~ 3.6 V
    Supplier-Device-Package 32-LQFP (7x7)
    Number-of-Taps-Steps 1024 Taps Steps
    Delay-to-1st-Tap 2.2ns
    Tap-Increment 10ps
    Available-Total-Delays 2.2ns ~ 12.2ns
    Number-of-Independent-Delays 1 Independent Delay
    Maximum Operating Temperature + 85 C
    Operating temperature range - 40 C
    Part-#-Aliases MC100EP195BMNG
    Supply-Voltage-Max +/- 3.6 V
    Supply-Voltage-Min +/- 3 V
  • Datasheet
    Not found or temporary maintenance
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Additional Information
  • Datasheet: Download MC100EP195FAG
  • Chipdatas Part: CD87-MC100EP195FAG
  • Warehouse: China, Hong Kong
  • Dispatch: Within 24 hours
  • Free Shipping: Yes
  • Prority Shipping: Yes, 3-5 days
  • Last Updated: 2024/06/12 08:21 +0800
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