SY100EP14UK4 - Brand New MIC Clock Buffers, Drivers
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Description
The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LVNECL. The delay varies in discrete steps based on a control word presented to SY100EP195V. The 10-bit width of this latched control register allows for delay increments of approximately 10ps.
Specifications and features
■ Pin-for-pin, plug-in compatible to the ON Semiconductor MC100EP195
■ Maximum frequency > 2.5GHz
■ Programmable range: 2.2ns to 12.2ns
■ 10ps increments
■ PECL mode operating range: VCC = 3.0V to 5.5V with VEE = 0V
■ NECL mode operating range: VCC = 0V with VEE = –3.0V to –5.5V
■ Open input default state
■ Safety clamp on inputs
■ A logic high on the /EN pin will force Q to logic low
■ D[0:10] can accept either ECL, CMOS, or TTL inputs
■ VBB output reference voltage
■ Available in a 32-pin TQFP packageApplication Scenarios
NoneComparison
NoneAdvantagesNoneDisadvantagesNone -
Similar parts: 2580 , Click to view
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
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Popular parts of the same kind
- Datasheet: Download SY100EP14UK4
- Chipdatas Part: CD88-SY100EP14UK4
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/10/01 14:00 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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The fee is charged according to the rule of PayPal.
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The fee is charged according to the rule of PayPal.
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Western Union charge US$0.00 banking fee.
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We recommend to use bank transfer for large orders to save on handling fees.
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