Description

Electronic Component Model: R8A77230AD400BGV
Product Category: IC Chips
This LSI is a single-chip RISC microprocessor that integrates a 32-bit RISC-type Super H architecture CPU with a digital signal processing (DSP) extension as its core, together with a large-capacity 32-kbyte cache memory, a 16-kbyte X/Y memory, and an interrupt controller. High-speed data transfers can be performed by an on-chip direct memory access controller (DMAC), and an external memory access support function enables direct connection to different kinds of memory. This LSI also supports a stereo audio recording and playback function, a USB host controller, a function controller, an LCD controller, a PCMCIA interface, an A/D converter, and a D/A converter.
The USB host controller and LCD controller have bus master functions, so that data supplied from an external memory (area 3) can be freely processed. Since the USB host controller, in particular, conforms to Open HCI standards, it is extremely easy to transfer data from the PC of a device driver or other devices. Also, low-power operation suitable for battery operation is possible because the LCD controller continues to display even in sleep mode.
A powerful built-in power management function keeps power consumption low, even during high-speed operation. This LSI is ideal for electronic devices that require both high speed and low power consumption.
The SH7720 group integrates an SSL (Secure Socket Layer) accelerator that performs RSA (Rivest-Shamir-Adleman) operations and DES (Data Encryption Standard) and Triple-DES encryption/decryption, while the SH7721 group does not have the SSL accelerator. Each group consists of several models which include or do not include an SD host interface (SDHI) to be suited to a variety of applications. See table 1.2 and 1.3, Product Lineup, for the models including (or not including) the SDHI.

Specifications and features

Features:
- Renesas Technology Original SuperH architecture
- Upper compatibility with SH-1, SH-2, and SH3-DSP at object code level
- 32-bit internal data bus
- General-register: Sixteen 32-bit general registers (eight 32-bit shadow registers)
- RISC type instruction set: Instruction length of 16-bit fixed length for improved code efficiency
- Instruction execution time of one instruction/cycle for basic instructions
- Logical address space of 4 Gbytes
- Space identifier ASID of 8 bits, 256 logical address spaces
- Five-stage pipeline

Application Scenarios

- Ideal for electronic devices that require both high speed and low power consumption
- Suitable for battery operation due to low-power operation
- Supports stereo audio recording and playback function, USB host controller, function controller, LCD controller, PCMCIA interface, A/D converter, and D/A converter
- Can transfer data easily from PC or other devices due to USB host controller conforming to Open HCI standards
- The LCD controller continues to display even in sleep mode
- Integrates an SSL accelerator that performs RSA operations and DES and Triple-DES encryption/decryption
- Different models available with or without an SD host interface (SDHI) for various applications

Comparison

Advantages:
- Integrates a 32-bit RISC-type Super H architecture CPU with a DSP extension
- Supports high-speed data transfers with an on-chip direct memory access controller (DMAC)
- Supports various functions such as stereo audio recording and playback, USB host controller, LCD controller, etc.
- Low-power operation suitable for battery operation
- Integrates an SSL accelerator for encryption/decryption operations (SH7720 group)
- Supports different models with or without an SD host interface (SDHI) for various applications
Disadvantages:
- The SH7721 group does not have the SSL accelerator
- Some features may not be available in models without an SD host interface (SDHI)