GTLP10B320MTD - Brand New onsemi Universal Bus Function
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General Description
The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
Features
■ Bidirectional interface between GTLP and LVTTL logic levels
■ Variable edge rate control pin to select desired edge rate on GTLP port (VERC)
■ VREF pin provides external supply reference voltage for receiver threshold adjustibility
■ Split LVTTL inputs and outputs
■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
■ A feedback path for control and diagnostics monitoring
■ TTL compatible driver and control inputs
■ Designed using Fairchild advanced BiCMOS technology
■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
■ Power up/down and power off high impedance for liveinsertion
■ Open drain on GTLP to support wired-or connection
■ Flow through pinout optimizes PCB layout
■ A Port source/sink −24mA/+24mA
■ B Port sink +50mA -
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Datasheet
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Shopping guide
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Popular parts of the same kind
- Datasheet: Download GTLP10B320MTD
- Chipdatas Part: CD89-GTLP10B320MTD
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/03 04:22 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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