Description

The MPC860PCZQ66D4 is a microprocessor that belongs to the PowerQUICC series, a one-chip integrated microprocessor and peripheral combination designed for a variety of controller applications, especially in communications and networking systems. This particular unit excels in both of these areas, referred to as the MPC860 in the manual.

Specifications and features

• CPU: The MPC860 quad-core with 32-bit general-purpose registers (GPRs) performs branch prediction with conditional prefetch, without conditional execution.
• Cache: Dynamic bus sizing for 8, 16, and 32 bits. 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache. Instruction and data caches are two-way, set-associative, physically addressed, LRU replacement, and lockable on-line granularity.
• Memory Controller: Eight banks, complete dynamic RAM (DRAM) controller, each bank can be a chip select, a RAS to support a DRAM bank, up to 15 wait states per memory bank. It has a Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices. The DRAM controller is programmable to support most size- and speed-memory interfaces.
• General-purpose timers: Four 16-bit timers or two 32-bit timers, gate mode can enable/disable counting, interrupt can be masked on reference match and event capture.
• Communication controllers: Four serial communications controllers (SCCs), two SMCs (serial management channels), one I2C (inter-integrated circuit) port, and one SPI (serial peripheral interface). The SCCs support HDLC/SDLC, asynchronous HDLC to support PPP (point-to-point protocol).
• PCMCIA interface: Master (socket) interface, release 2.1 compliant, supports two independent PCMCIA sockets.
• Low Power Support: Full on, Doze, Sleep, Deep sleep, Power down mode.
• Debug Interface: Eight comparators, supports conditions: = ≠ <>, each watchpoint can generate a breakpoint internally.
• Package type: 357-pin ball grid array (BGA) package.

Application Scenarios

The MPC860PCZQ66D4 microprocessor is used as an embedded single-issue, 32-bit MPC8xx core implementing the PowerPC architecture and finds its best applications in communications and networking systems, as it excels in both areas.

Comparison

• Excellent for networking and communication systems due to its unique combination of microprocessor and peripheral design.
• Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks.
• The cache is physically addressed, implements a least recently used (LRU) replacement algorithm, and is lockable on a cache block basis.

• It is difficult to use without adequate technical knowledge and proficiency, which can make it challenging for beginners.
• It may be costly compared to other microprocessors in the market, which may not make it the ideal choice for budget-oriented applications.