Description

The PM7305A-BGI is a monolithic integrated circuit, specifically designed to handle ATM layer functions. It serves as a routing control, monitoring, and policing device with a sustained aggregate throughput of 0.355x10^6 cells/s. This device is intended to be placed between a switch core and physical layer devices in the ingress direction. It supports up to 65536 connections and utilizes external SRAM for per-VPI/VCI data structures.

Specifications and features

- Monolithic single chip device for ATM switch ingress VPI/VCI address translation, cell appending, cell rate policing, counting, and OAM requirements for 65,536 VCs

- Instantaneous transfer rate of 200 Mbit/s, supporting a cell transfer rate of 0.355x10^6 cells/s (one STS-3c)

- Concentrates traffic from multiple PHY interfaces into one switch port

- 8 bit PHY interface compatible with Utopia Level 1 cell-level handshake, supporting direct addressing for up to 4 PHYs, and Multi-PHY addressing for up to 32 PHYs (Utopia Level 2 compatible)

- 8 bit extended cell format SCI-PHY interface at output to switch fabric, supporting 52-64 byte extended ATM cell with prepend/postpend

- Compatible with a wide range of switching fabrics and traffic management architectures

- Provides identification/tagging of RM (Resource Management) cells to support adjunct processing applications such as Virtual Source/Virtual Destination ABR (Available Bit Rate) service

- Supports logical multicast

- Flexible CAM-type cell identification using arbitrary VPI/VCI values and/or cell appended bytes

- Discards low priority (high CLP bit) cells on command to relieve switch congestion

- Can discard or tag the remainder of an AAL5 packet if a single cell in that packet is discarded or tagged due to policing

- Includes a 16-bit FIFO buffered microprocessor bus interface for cell extraction and insertion, VC table access, control and status monitoring, and device configuration

- Supports DMA (Direct Memory Access) access for cell extraction and insertion

- Uses common synchronous SRAMs for maintaining per-VC (Virtual Circuit) information

- Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes

- Provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring

- Low power, 0.6-micron, +5 Volt CMOS technology

- 240 copper slugged plastic quad flat pack (PQFP) package

Application Scenarios

- ATM Hubs and Workgroup Switches

- ATM Enterprise, Edge, and Access Switches

Comparison

- Monolithic single-chip device with a high transfer rate of 200 Mbit/s

- Supports a wide range of switching fabrics and traffic management architectures

- Provides flexible cell identification and tagging options

- Limited to a maximum of 65536 connections