Description

The PM5365-PI is an electronic component belonging to the category of IC chips. It is a feature-rich device that finds utility in high density link termination over T1 channelized DS3 or T1 and E1 channelized SONET/SDH facilities. This device comprises a SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous mapper, a full-featured M13 multiplexer with DS3 framer, and a SONET/SDH DS3 mapper in a single monolithic device. It terminates DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams.

Specifications and features

• Integrates a SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous mapper, a full featured M13 multiplexer with DS3 framer, and a SONET/SDH DS3 mapper in a single monolithic device for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams
• Provides five fundamental modes of operation
• Provides jitter attenuation in the T1 or E1 receive and transmit directions
• Provides two independent de-jittered T1 or E1 recovered clocks for system timing and redundancy
• Provides an on-board programmable binary sequence generator and detector for error testing at DS3 rates. Includes support for patterns recommended in ITU-T O.151
• Provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and O.152
• Supports the M23 and C-bit parity DS3 formats
• Standalone unchannelized DS3 framer mode for access to the entire DS3 payload
• Low power 2.5V/3.3V CMOS technology. All pins are 5V tolerant
• 324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial temperature range (-40°C to 85°C) operation

Application Scenarios

The PM5365-PI IC chip finds applications in SONET/SDH Add Drop Multiplexers, SONET/SDH Terminal Multiplexers, M23 Based M13 Multiplexer, C-Bit Parity-Based M13 Multiplexer, and Channelized and Unchannelized DS3 Frame Relay Interfaces.

Comparison

• Provides a SONET/SDH Add/Drop bus interface with integrated VT1.5, TU- 11, VT2 and TU-12 mapper for T1and E1 streams. Also provides a DS3 mapper
• Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes

• It requires that the STS-3/STM-1 be in locked mode such that the J1 bytes immediately follow the C1 bytes
• An external oscillator or receive side clock (loop-timed) is required for DS3 transmit clock source selection