QL2003-OPF100C - Brand New IC Chips
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PRODUCT SUMMARY
The QL2003 is a 3,000 usable ASIC gate, 5,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.
FEATURES
Ultimate Verilog/VHDL Silicon Solution
- Abundant, high-speed interconnect eliminates manual routing
- Flexible logic cell provides high efficiency and performance
- Design tools produce fast, efficient Verilog/VHDL synthesisSpeed, Density, Low Cost and Flexibility in One Device
- 16-bit counter speeds exceeding 200 MHz
- 3,000 usable ASIC gates, 5,000 usable PLD gates, 118 I/Os
- 3-layer metal ViaLink® process for small die sizes
- 100% routable and pin-out maintainableAdvanced Logic Cell and I/O Capabilities
- Complex functions (up to 16 inputs) in a single logic cell
- High synthesis gate utilization from logic cell fragments
- Full IEEE Standard JTAG boundary scan capability
- Individually-controlled input/feedback registers and OEs on all I/O pinsOther Important Family Features
- 3.3V and 5.0V operation with low standby power
- I/O pin-compatibility between different devices in the same packages
- PCI compliant (at 5.0V), full speed 33 MHz implementations
- High design security provided by security fusesTotal of 118 I/O Pins
- 110 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pinsFour Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedbackHigh Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz -
Similar parts: 430483 , Click to view
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
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- - EMS: 10-15 business days
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DHL, FedEx, EMS, SF Express, and Registered Air MailShipping tracking:
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Popular parts of the same kind
- Datasheet: Download QL2003-OPF100C
- Chipdatas Part: CD89-QL2003-OPF100C
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/13 16:44 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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Western Union charge US$0.00 banking fee.
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