Description

Electronic Component Model:PM7350-PGI

Product Category:IC Chips

Specifications and features

• Integrated analog/digital device that interfaces a high-speed parallel bus to a high speed Low Voltage Differential Signal (LVDS) serial link with optional 1:1 protection.
• For framers or modems without Utopia bus interfaces the S/UNI-DUPLEX provides cell delineation (I.432) across 16 clock and data (bit serial) interfaces.
• Fault detection, redundancy, protection switching, and inserting/removing cards while the system is running (hot swap).
• Interface to other S/UNI-DUPLEX or S/UNI-VORTEX, to satisfy a full set of system level requirements for backplane interconnect:
• Transports user data by providing the inter-card data-path.
• Inter-processor communication by providing an integrated inter-card control channel.
• Exchanges flow control information (back-pressure) to prevent data loss.
• Provides embedded command and control signals across the backplane: system reset, error indications, protection switching commands, etc.
• Clock/timing distribution (system clocks as well as reference clocks such as 8 kHz timing references).
• When used as a parallel bus slave device, can be configured to share the bus with other S/UNI-DUPLEX bus slave devices.
• Can interface to another S/UNI-DUPLEX device (via a single LVDS link) to create a simple point-to-point "Utopia bus extension" capability.
• Can interface to two S/UNI-DUPLEX devices to create a 1:1 protected bus extension.
• Interworks with PM7351 S/UNI-VORTEX devices to implement a point-to multipoint serial backplane architecture, with optional 1:1 protection of the common card.
• In the LVDS receive direction: selects traffic from the LVDS link marked active and demultiplexes the individual cell streams to the appropriate PHY device.
• Cell read/write to both LVDS links available through the processor port. Provides optional hardware assisted CRC32 calculation across cells to support an embedded inter-processor communication channel across the LVDS links.
• Requires no external memories.
• Standard 5 pin P1149.1 JTAG test port.
• Low-power, 3.3V CMOS technology.
• 160-pin high-performance plastic ball grid array (PBGA) package.

Application Scenarios

• Single shelf or multi-shelf Digital Subscriber Loop Access Multiplexer (DSLAM).
• ATM, frame relay, IP switch.
• Multiservice access multiplexer.
• Universal Mobile Telecommunication System (UMTS) wireless base stations.
• 16 channel cell delineation (I.432 transmission convergence processing).