Functional Description

The CY2DP1510 is an ultra-low noise, low skew, low-propagation delay 1:10 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1510 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.

Features

■ Select one of two low-voltage positive emitter-coupled logic (LVPECL) input pairs to distribute to 10 LVPECL output pairs
■ 40-ps maximum output-to-output skew
■ 600-ps maximum propagation delay
■ 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
■ Up to 1.5-GHz operation
■ 32-Pin thin quad flat pack (TQFP) package
■ 2.5-V or 3.3-V operating voltage[1]
■ Commercial and industrial operating temperature range