Description

The C2520C-39NK is an IC chip, specifically a low-skew, low-jitter, phase-locked loop (PLL) clock driver designed for networking applications. It provides a low-noise clock signal that can be distributed across 5 banks of 4 clocks and includes an extra clock for feedback. Additionally, the C2520C-39NK features a zero input-to-output delay, maximum clock frequency of 125 MHz, low jitter, and on-chip series damping resistor at clock output drivers for low noise and EMI reduction. It operates at 3.3V VCC and comes in a plastic 56-pin TSSOP (A) package.

Specifications and features

• Low-Noise Phase-Locked Loop Clock Distribution
• Allows Clock Input to have Spread Spectrum modulation for EMI reduction. The clock outputs track the Clock Input modulation
• Maximum clock frequency of 125 MHz
• Zero Input-to-Output delay
• Low jitter: Cycle-to-Cycle jitter –100ps max
• On-chip series damping resistor at clock output drivers for low noise and EMI reduction
• Operates at 3.3V VCC
• Output-to-Output skew less than 200ps
• Package: Plastic 56-pin TSSOP (A)

Application Scenarios

The C2520C-39NK is designed for use in networking applications, specifically in distributing low-noise clock signals.

Comparison

• Low-noise clock distribution
• Low input-to-output skew
• On-chip series damping resistor for EMI reduction
• Allows Clock Input to have Spread Spectrum modulation for EMI reduction

• Limited to a maximum clock frequency of 125 MHz