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Description
The L800DB90VI is an electronic component model in the IC Chips product category. It is an 8 Mbit, 3.0 volt-only Flash memory that is organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. It requires only a single 3.0 volt VCC supply for read, program, and erase operations. The L800DB90VI can also be programmed and erased using a standard EPROM programmer.
Specifications and features
- Single power supply operation: 2.7 to 3.6 volt read and write operations for battery-powered applications
- Manufactured on 0.23 µm process technology
- High performance: Access times as fast as 70 ns
- Ultra low power consumption: 200 nA Automatic Sleep mode current, 200 nA standby mode current, 7 mA read current, 15 mA program/erase current
- Flexible sector architecture: One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode), One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode), Supports full chip erase
- Sector Protection features: hardware method of locking a sector to prevent any program or erase operations within that sector, sectors can be locked in-system or via programming equipment, temporary Sector Unprotect feature allows code changes in previously locked sectors
- Unlock Bypass Program Command: reduces overall programming time when issuing multiple program command sequences
- Top or bottom boot block configurations available
- Embedded Algorithms: Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors, Embedded Program algorithm automatically writes and verifies data at specified addresses
- Minimum 1 million write cycle guarantee per sector
- 20-year data retention at 125°C: reliable operation for the life of the system
- Compatibility with JEDEC standards: pinout and software compatible with single power supply Flash, superior inadvertent write protection
- Data# Polling and toggle bits: provides a software method of detecting program or erase operation completion
- Ready/Busy# pin (RY/BY#): provides a hardware method of detecting program or erase cycle completion
- Erase Suspend/Erase Resume: suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
- Hardware reset pin (RESET#): hardware method to reset the device to reading array data
Application Scenarios
The L800DB90VI is suitable for a wide range of applications including battery-powered devices, systems that require high performance and low power consumption, and applications that require flexible sector architecture and data protection. It is also compatible with JEDEC standards, making it easy to integrate into existing systems.
Comparison
Advantages- Single power supply operation
- High performance with fast access times
- Ultra low power consumption
- Flexible sector architecture
- Compatibility with JEDEC standards
- Data protection features
DisadvantagesNo specific disadvantages have been identified for the L800DB90VI model.
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Similar parts: 430483 , Click to view
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Datasheet
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Shopping guide
Delivery period:
- - Will ship out in 2-3 days
- - DHL Express: 3-7 business days
- - DHL eCommerce: 12-22 business days
- - FedEx International Priority: 3-7 business days
- - EMS: 10-15 business days
Shipping fee:
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Shipping option:
DHL, FedEx, EMS, SF Express, and Registered Air MailShipping tracking:
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How to Buy:
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Additional Information
- Datasheet: Download l800DB90VI
- Chipdatas Part: CD92-l800DB90VI
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/13 05:52 +0800
Refund
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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Payment Method
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Western Union charge US$0.00 banking fee.
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