DEVICE OVERVIEW

This document contains device-specific information for the following devices:
• ENC424J600
• ENC624J600

**The ENC424J600 and ENC624J600 are stand-alone, Fast Ethernet

controllers with an industry standard Serial Peripheral Interface (SPI) or a flexible parallel interface. They are designed to serve as an Ethernet network interface for any microcontroller equipped with SPI or a standard parallel port.**

ENC424J600/624J600 devices meet all of the IEEE 802.3 specifications applicable to 10Base-T and 100Base-TX Ethernet, including many optional clauses, such as auto-negotiation. They incorporate a number of packet filtering schemes to limit incoming packets. They also provide an internal, 16-bit wide DMA for fast data throughput and support for hardware IP checksum calculations.
For applications that require the security and authentication features of SSL, TLS and other protocols related to cryptography, a block of security engines is provided. The engines perform RSA, Diffie-Hellman, AES, MD5 and SHA-1 algorithm computations, allowing reduced code size, faster connection establishment and throughput, and reduced firmware development effort.

• IEEE 802.3™ Compliant Fast Ethernet Controller

• Integrated MAC and 10/100Base-T PHY
• Hardware Security Acceleration Engines
• 24-Kbyte Transmit/Receive Packet Buffer SRAM
• Supports one 10/100Base-T Port with Automatic
Polarity Detection and Correction
• Supports Auto-Negotiation
• Support for Pause Control Frames, including
Automatic Transmit and Receive Flow Control
• Supports Half and Full-Duplex Operation
• Programmable Automatic Retransmit on Collision
• Programmable Padding and CRC Generation
• Programmable Automatic Rejection of Erroneous
and Runt Packets
• Factory Preprogrammed Unique MAC Address
• MAC:
- Support for Unicast, Multicast and Broadcast
packets
- Supports promiscuous reception
- Programmable pattern matching
- Programmable filtering on multiple packet
formats, including Magic Packet™, Unicast,
Multicast, Broadcast, specific packet match,
destination address hash match or any packet
• PHY:
- Wave shaping output filter
- Internal Loopback mode
- Energy Detect Power-Down mode
• Available MCU Interfaces:
- 14 Mbit/s SPI interface with enhanced set of
opcodes (44-pin and 64-pin packages)
- 8-bit multiplexed parallel interface
(44-pin and 64-pin packages)
- 8-bit or 16-bit multiplexed or demultiplexed
parallel interface (64-pin package only)
• Security Engines:
- High-performance, modular exponentiation
engine with up to 1024-bit operands
- Supports RSA® and Diffie-Hellman key
exchange algorithms
- High-performance AES encrypt/decrypt
engine with 128-bit, 192-bit or 256-bit key
- Hardware AES ECB, CBC, CFB and OFB
mode capability
- Software AES CTR mode capability
- Fast MD5 hash computations
- Fast SHA-1 hash computations
• Buffer:
- Configurable transmit/receive buffer size
- Hardware-managed circular receive FIFO
- 8-bit or 16-bit random and sequential access
- High-performance internal DMA for fast
memory copying
- High-performance hardware IP checksum
calculations
- Accessible in low-power modes
- Space can be reserved for general purpose
application usage in addition to transmit and
receive packets
• Operational:
- Outputs for two LED indicators with support
for single and dual LED configurations
- Transmit and receive interrupts
- 25 MHz clock
- 5V tolerant inputs
- Clock out pin with programmable frequencies
from 50 kHz to 33.3 MHz
- Operating voltage range of 3.0V to 3.6V
- Temperature range: -40°C to +85°C industrial
• Available in 44-Pin (TQFP and QFN) and 64-Pin
TQFP Packages