Description

The Electronic Component Model EPM78P447SBPS-G is a high-density, high-performance programmable logic device (PLD) based on Altera’s second-generation MAX architecture. This device is part of the MAX 7000 family and is fabricated with advanced CMOS technology. It provides 600 to 5,000 usable gates, in-system programmability (ISP), and pin-to-pin delays as fast as 5 ns. It also offers counter speeds of up to 175.4 MHz. The MAX 7000S devices in different speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Specifications and features

The EPM78P447SBPS-G features high-performance, EEPROM-based programmable logic devices (PLDs) with 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. It includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices. The device has built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells. It has a complete EPLD family with logic densities ranging from 600 to 5,000 usable gates. The device also offers 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies and open-drain output options in MAX 7000S devices.

Application Scenarios

The Electronic Component Model EPM78P447SBPS-G is suitable for various applications such as logic design, digital circuit design, and programmable logic controllers. It can be used in industries that require high-performance programmable logic devices with in-system programmability.

Comparison

• High-density and high-performance programmable logic device
• Advanced CMOS technology
• In-system programmability (ISP)
• Compliance with PCI Local Bus Specification
• Wide range of logic densities

• Not suitable for low-voltage applications
• Limited pin options in certain packages