PCA9517DP118 - Brand New NXP Semiconductors Signal Buffers, Repeaters, Splitters
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Description
The PCA9517DP118 is a CMOS integrated circuit that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications. It enables the system designer to isolate two halves of a bus for both voltage and capacitance. The PCA9517DP118 features bidirectional buffering for both the data (SDA) and the clock (SCL) lines, allowing for two buses of 400 pF. The SDA and SCL pins are high-impedance when the PCA9517DP118 is unpowered. It is compatible with I2C-bus and SMBus and supports arbitration and clock stretching across the repeater. The operating supply voltage range for the A-side is 0.9 V to 5.5 V, and for the B-side is 2.7 V to 5.5 V. The PCA9517DP118 is available in SO8 and TSSOP8 packages.
Specifications and features
- 2 channel, bidirectional buffer isolates capacitance
- Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
- Footprint and functional replacement for PCA9515/15A
- I2C-bus and SMBus compatible
- Active HIGH repeater enable input
- Open-drain input/outputs
- Lock-up free operation
- Supports arbitration and clock stretching across the repeater
- Accommodates Standard mode and Fast mode I2C-bus devices and multiple masters
- Powered-off high-impedance I2C-bus pins
- 5 V tolerant I2C-bus and enable pins
- 0 Hz to 400 kHz clock frequency
- ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
- Packages offered: SO8 and TSSOP8
Application Scenarios
The PCA9517DP118 is commonly used in signal buffering, repeating, and splitting applications for level shifting in I2C-bus or SMBus systems. It is suitable for various electronic devices and can be used in scenarios where voltage level translation and high-impedance I2C-bus pins are required.
Comparison
Advantages- Allows level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications
- Enables isolation of two halves of a bus for both voltage and capacitance
- Provides bidirectional buffering for both the data (SDA) and the clock (SCL) lines, allowing for two buses of 400 pF
- Compatible with I2C-bus and SMBus
- Supports arbitration and clock stretching across the repeater
- Powered-off high-impedance I2C-bus pins
- ESD protection exceeds industry standards
Disadvantages- Static offset design of the B-side drivers prevents connection to certain devices
- Output pull-down on the B-side internal buffer LOW is set for approximately 0.5 V
- Operating supply voltage range for the A-side is limited to 0.9 V to 5.5 V
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Datasheet
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- Datasheet: Download PCA9517DP118
- Chipdatas Part: CD88-PCA9517DP118
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- Last Updated: 2024/06/03 07:39 +0800
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