Description

The A80960CF40 is a 32-bit high-performance superscalar processor that is socket and object code compatible with the 80960CA. It has a load/store architecture, sixteen 32-bit global registers, sixteen 32-bit local registers, and manipulates 64-bit bit fields. This model features four on-chip DMA channels that transfer data at 59 Mbytes/s and a demultiplexed 32-bit burst bus with pipelining. It also has a fast procedure call/return model and on-chip caches for instructions and data.

Specifications and features

• 32-bit high-performance superscalar processor
• Socket and object code compatible with 80960CA
• Two instructions/clock sustained execution
• Four 59 Mbytes/s DMA channels with data chaining
• Demultiplexed 32-bit burst bus with pipelining
• 32-bit parallel architecture with load/store architecture
• Sixteen 32-bit global registers and sixteen 32-bit local registers
• Manipulates 64-bit bit fields and has 11 addressing modes
• Full parallel fault model and supervisor protection model
• Fast procedure call/return model with full procedure call in 4 clocks
• On-chip register cache caches registers on call/ret
• Minimum of 6 frames provided and up to 15 programmable frames
• On-chip instruction cache with 4 Kbyte two-way set associative and cache-lock modes, cache-off mode
• On-chip data cache with 1 Kbyte direct-mapped, write through and 128 bits per clock access on cache hit
• Product grades available: SE3: -40°C to +110°C
• High bandwidth on-chip data RAM with 1 Kbytes on-chip RAM for data and sustain 128 bits per clock access
• Four on-chip DMA channels with 59 Mbytes/s fly-by transfers, 32 Mbytes/s two-cycle transfers, data chaining, data packing/unpacking, and programmable priority method
• 32-bit demultiplexed burst bus with 128-bit internal data paths to and from registers, burst bus for DRAM interfacing, address pipelining option, fully programmable wait states, supports 8, 16 or 32-bit bus widths, supports unaligned accesses, and supervisor protection pin
• Selectable big or little endian byte ordering
• High-speed interrupt controller with up to 248 external interrupts, 32 fully programmable priorities, multi-mode 8-bit interrupt port, four internal DMA interrupts, separate, non-maskable interrupt pin, and context switch in 750 ns typical

Application Scenarios

The A80960CF40 can be used as the central processing unit in a variety of electronic devices, including industrial control and monitoring systems, network routers and switches, telecommunications equipment, and automobile engine control units.

Comparison

• 32-bit parallel architecture with load/store architecture and manipulating 64-bit bit fields
• On-chip caches for instructions and data
• Four on-chip DMA channels with data chaining and high bandwidth on-chip data RAM
• 32-bit demultiplexed burst bus with pipelining
• Selectable big or little endian byte ordering
• High-speed interrupt controller with up to 248 external interrupts and 32 fully programmable priorities

• May not be suitable for use in small electronic devices due to its size and power consumption