Description

The PM8351-PC is an electronic component in the IC Chips category, specifically an OctalPHYTM. It is an eight-channel Physical Layer Transceiver with eight independent serial channels that operate at up to 1.25 Gbps. It includes 8B/10B block coding logic and produces run length limited data streams for serial transmission.

Specifications and features

• Eight independent 1.0-1.25 Gbit/s transceivers
• Ultra low power operation: 1.25 Watts typical
• Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic
• Physical Coding Sublayer (PCS) logic for Gigabit Ethernet
• Dual Data Rate (DDR) parallel interface with clock forwarding to halve ASIC terminal count and simplify timing
• Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface
• Built-in packet generator/checker
• “Trunking” feature to de-skew and align received parallel data across eight channels
• IEEE 1149.1 JTAG testing support
• IEEE 802.3z Gigabit Ethernet and ANSI X3T11 FibreChannel support
• High speed outputs which feature programmable output current to directly drive dual-terminated line
• 2.5 V, 0.25 µ CMOS technology with 3.3V tolerant I/O
• Direct interface to optical modules, coax, or serial backplanes
• Small footprint 19x19 mm, 289-pin PBGA

Application Scenarios

The PM8351-PC is ideal for systems requiring large numbers of point-to-point gigabit links, such as high-speed serial backplanes, Gigabit Ethernet links, FibreChannel links, intra-system interconnects, and ASIC to PMD links.

Comparison

• Eight independent serial channels capable of operation at up to 1.25 Gbps
• Ultra low power consumption of 1.25 Watts typical
• Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic
• Physical Coding Sublayer (PCS) logic for Gigabit Ethernet support
• Built-in packet generator/checker for testing
• Dual Data Rate (DDR) parallel interface with clock forwarding to halve ASIC terminal count and simplify timing
• Direct interface to optical modules, coax, or serial backplanes

• Not suitable for systems that require fewer point-to-point gigabit links
• Requires an external MDC/MDIO serial interface for controlling loopback, BIST, and operating modes
• Requires a programmer for IEEE 1149.1 JTAG testing