OR4E02-2BM680C-1I - Brand New LATTICE IC Chips
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Description
Electronic Component Model: OR4E02-2BM680C-1I
Product Category: IC Chips
Architecture Overview: The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lucent Technologies Microelectronics Group. It includes enhancements and innovations geared toward today’s high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades.
Specifications and features
- High-performance platform design
- 0.13 µm seven-level metal technology
- Internal performance of >250 MHz (four logic levels)
- I/O performance of >416 MHz for all user I/Os
- Over 1.5 million usable system gates
- Meets multiple I/O interface standards
- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance
- Embedded block RAM (EBR) for onboard storage and buffer needs
- Built-in system components including an internal system bus, eight PLLs, and microprocessor interface
- Traditional I/O selections
- LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os
- Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance
- Individually programmable drive capability. 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source
- Two slew rates supported (fast and slew-limited)
- Fast-capture input latch and input flip-flop (FF)/ latch for reduced input setup time and zero hold time
- Fast open-drain drive capability
- Capability to register 3-state enable signal
- Off-chip clock drive capability
- Two-input function generator in output path
- New programmable high-speed I/O
- Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), zero-bus turn-around (ZBT*), and double data rate (DDR)
- Double-ended: LDVS, bused-LVDS, LVPECL
- Customer defined: Ability to substitute arbitrary standard-cell I/O to meet fast moving standards
- New capability to (de)multiplex I/O signals
- New DDR on both input and output at rates up to 311 MHz (622 MHz effective rate)
- Used to implement emerging RapidIO† backplane interface specification
- New 2x and 4x downlink and uplink capability per I/O (i.e., 104 MHz internal to 416 MHz I/O)
- Enhanced twin-quad programmable function unit (PFU)
- Eight 16-bit look-up tables (LUTs) per PFU
- Nine user registers per PFU, one following each LUT and organized to allow two nibbles to act independently, plus one extra for arithmetic carry/borrow operations
Application Scenarios
This electronic component model can be used in various networking applications that require high-speed systems. It is designed to reduce logic requirements and increase system speed. It is suitable for applications where performance, I/O interface standards, and system-level features are critical.
Comparison
Advantages- New generation architecture with enhanced features
- Multiple I/O interface standards supported
- High-performance platform design
- 1.5 V operation for greater performance
- Built-in system components for easier integration
Disadvantages- May require expertise in programming and configuration
- Packages and speed grades may vary
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Shopping guide
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Additional Information
- Datasheet: Download OR4E02-2BM680C-1I
- Chipdatas Part: CD94-OR4E02-2BM680C-1I
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/03 13:14 +0800
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- Full Refund if you don't receive your order
- Full or Partial Refund , If the item is not as described
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