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GENERAL DESCRIPTION
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURES
● JEDEC standard 3.3V power supply
● LVTTL compatible with multiplexed address
● Four banks operation
● MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
● All inputs are sampled at the positive going edge of the system clock
● DQM for masking
● Auto & self refresh
● 64ms refresh period (4K cycle)
- 15.6 μ s refresh interval -
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Datasheet
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Popular parts of the same kind
- Datasheet: Download M12L6416A-7T
- Chipdatas Part: CD93-M12L6416A-7T
- Warehouse: China, Hong Kong
- Dispatch: Within 24 hours
- Free Shipping: Yes
- Prority Shipping: Yes, 3-5 days
- Last Updated: 2024/06/03 12:48 +0800
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